Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 RAS updates from Ingo Molnar:
 "The main changes in this development cycle were:

   - more AMD northbridge support work, mostly in preparation for Fam17h
     CPUs (Yazen Ghannam, Borislav Petkov)

   - cleanups/refactorings and fixes (Borislav Petkov, Tony Luck,
     Yinghai Lu)"

* 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mce: Include the PPIN in MCE records when available
  x86/mce/AMD: Add system physical address translation for AMD Fam17h
  x86/amd_nb: Add SMN and Indirect Data Fabric access for AMD Fam17h
  x86/amd_nb: Add Fam17h Data Fabric as "Northbridge"
  x86/amd_nb: Make all exports EXPORT_SYMBOL_GPL
  x86/amd_nb: Make amd_northbridges internal to amd_nb.c
  x86/mce/AMD: Reset Threshold Limit after logging error
  x86/mce/AMD: Fix HWID_MCATYPE calculation by grouping arguments
  x86/MCE: Correct TSC timestamping of error records
  x86/RAS: Hide SMCA bank names
  x86/RAS: Rename smca_bank_names to smca_names
  x86/RAS: Simplify SMCA HWID descriptor struct
  x86/RAS: Simplify SMCA bank descriptor struct
  x86/MCE: Dump MCE to dmesg if no consumers
  x86/RAS: Add TSC timestamp to the injected MCE
  x86/MCE: Do not look at panic_on_oops in the severity grading

1 files changed, 4 insertions, 2 deletions

diff --git a/str.c b/str.c
index cfee03f..532058a 100644
--- a/str.c
+++ b/str.c
@@ -97,11 +97,13 @@ char *argv2str(int startind, int argc, char **argv)
 	int ret, i;
 
 	for (i = startind; i < argc; ++i) {
-		size_t alen = strlen(argv[i]) + 2;
+		size_t tlen = (i < argc - 1) ? 2 : 1;
+		size_t alen = strlen(argv[i]) + tlen;
 		size_t slen = str ? strlen(str) : 0;
 
 		str = xrealloc(str, slen + alen);
-		ret = slprintf(str + offset, strlen(argv[i]) + 2, "%s ", argv[i]);
+		ret = slprintf(str + offset, strlen(argv[i]) + tlen, "%s%s",
+				argv[i], tlen == 2 ? " " : "");
 		if (ret < 0)
 			panic("Cannot concatenate string!\n");
 		else