RealView boards with certain revisions of the L220 cache controller (ARM11*
processors only) may have issues (hardware deadlock) with the recent changes to
the mb() barrier implementation (DSB followed by an L2 cache sync). The patch
redefines the RealView ARM11MPCore mandatory barriers without the outer_sync()
call.

Cc: <stable@kernel.org>
Tested-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 1 insertions, 1 deletions

diff --git a/Makefile b/Makefile
index bcb8cd4..cfa1402 100644
--- a/Makefile
+++ b/Makefile
@@ -4,7 +4,7 @@
 #
 # Licensed under the terms of the GNU General Public License; version 2 or later.
 
-VERSION	= 0.4
+VERSION	= 0.5
 
 # Paths
 prefix	= /usr/local