diff options
Diffstat (limited to 'dionysos_top.vhd')
-rw-r--r-- | dionysos_top.vhd | 38 |
1 files changed, 36 insertions, 2 deletions
diff --git a/dionysos_top.vhd b/dionysos_top.vhd index 6924a30..88f8e1f 100644 --- a/dionysos_top.vhd +++ b/dionysos_top.vhd @@ -99,6 +99,24 @@ entity dionysos_top is dram_ba1_n_o : out std_logic; --! SDRAM Bank Address 0 --@} + --!@name ISP1362 Interface + --@{ + --! \anchor isp1362_grp + otg_d_io : inout std_logic_vector(15 downto 0); --! ISP1362 Data bus 16 Bits + otg_a_o : out std_logic_vector(1 downto 0); --! ISP1362 Address 2 Bits + otg_cs_n_o : out std_logic; --! ISP1362 Chip Select + otg_oe_n_o : out std_logic; --! ISP1362 Write + otg_we_n_o : out std_logic; --! ISP1362 Read + otg_reset_n_o : out std_logic; --! ISP1362 Reset + otg_int0_i : in std_logic; --! ISP1362 Interrupt 0 + otg_int1_i : in std_logic; --! ISP1362 Interrupt 1 + otg_dreq0_i : in std_logic; --! ISP1362 DMA Request 0 + otg_dreq1_i : in std_logic; --! ISP1362 DMA Request 1 + otg_dack0_n_o : out std_logic; --! ISP1362 DMA Acknowledge 0 + otg_dack1_n_o : out std_logic; --! ISP1362 DMA Acknowledge 1 + usb_clk_i : in std_logic; --! 12MHz USB clock + --@} + --!@name Flash Interface --@{ --! \anchor flash_grp @@ -387,7 +405,8 @@ architecture rtl of dionysos_top is reset_n => reset_nios_n, -- sdram_0 - zs_addr_from_the_sdram_0 => dram_a_o(11 downto 0), -- dram_a_o(12) is for 32Mbit SDRAM + zs_addr_from_the_sdram_0 => dram_a_o(12 downto 0), -- 64MB +-- zs_addr_from_the_sdram_0 => dram_a_o(11 downto 0), -- 16MB zs_ba_from_the_sdram_0 => dram_ba, zs_cas_n_from_the_sdram_0 => dram_cas_n_o, zs_cke_from_the_sdram_0 => dram_cke_o, @@ -439,7 +458,22 @@ architecture rtl of dionysos_top is rx_clk_to_the_tse_mac => pll_clk_25, set_1000_to_the_tse_mac => '0', -- tie to 0 if not used set_10_to_the_tse_mac => '0', -- tie to 0 if not used - tx_clk_to_the_tse_mac => pll_clk_25 + tx_clk_to_the_tse_mac => pll_clk_25, + + -- ISP1362 USB OTG controller + OTG_ADDR_from_the_ISP1362 => otg_a_o, + OTG_CS_N_from_the_ISP1362 => otg_cs_n_o, + OTG_DACK0_N_from_the_ISP1362 => otg_dack0_n_o, + OTG_DACK1_N_from_the_ISP1362 => otg_dack1_n_o, + OTG_DATA_to_and_from_the_ISP1362 => otg_d_io, + OTG_FSPEED_from_the_ISP1362 => open, + OTG_LSPEED_from_the_ISP1362 => open, + OTG_RD_N_from_the_ISP1362 => otg_oe_n_o, + OTG_RST_N_from_the_ISP1362 => otg_reset_n_o, + OTG_WR_N_from_the_ISP1362 => otg_we_n_o, + OTG_INT0_to_the_ISP1362 => otg_int0_i, + OTG_INT1_to_the_ISP1362 => otg_int1_i + ); --------------------------------------------------------------------- |