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+------------------------------------------------------------------
+-- _____ ______ _____ -
+-- |_ _| | ____|/ ____| Institute of Embedded Systems -
+-- | | _ __ | |__ | (___ Zuercher Hochschule fuer -
+-- | | | '_ \| __| \___ \ angewandte Wissenschaften -
+-- _| |_| | | | |____ ____) | (University of Applied Sciences) -
+-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland -
+------------------------------------------------------------------
+--
+-- Project : SInet
+-- Module : synthesis library ines_misc
+-- Description : input synchronisytion
+--
+-- $LastChangedDate $
+-- $Rev$
+-- $Author$
+-----------------------------------------------------------------
+--
+-- Change History
+-- Date |Name |Modification
+-----------------------------------------------------------------
+-- 01.02.08 | ffar + beut | file created based on library component
+-----------------------------------------------------------------
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+package input_sync_pkg is
+ component input_sync
+ generic(
+ G_INIT_VALUE : std_logic := '0'
+ );
+ port(
+ clk_i : in std_logic;
+ reset_n_i : in std_logic;
+ async_signal_i : in std_logic;
+ sync_signal_o : out std_logic
+ );
+ end component input_sync;
+end package input_sync_pkg;
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+entity input_sync is
+ generic(
+ G_INIT_VALUE : std_logic := '0'
+ );
+ port(
+ clk_i : in std_logic;
+ reset_n_i : in std_logic;
+ async_signal_i : in std_logic;
+ sync_signal_o : out std_logic
+ );
+ end input_sync;
+
+architecture rtl of input_sync is
+
+ signal sync_signal_f : std_logic;
+
+begin
+ sync_prc : process(clk_i, reset_n_i, async_signal_i, sync_signal_f)
+ begin
+ if reset_n_i = '0' then
+ sync_signal_f <= G_INIT_VALUE;
+ sync_signal_o <= G_INIT_VALUE;
+ elsif clk_i'event and clk_i = '1' then
+ sync_signal_f <= async_signal_i;
+ sync_signal_o <= sync_signal_f;
+ end if;
+ end process sync_prc;
+end rtl; \ No newline at end of file