diff options
Diffstat (limited to 'quartus/dionysos_nios2mmu.qsf')
| -rw-r--r-- | quartus/dionysos_nios2mmu.qsf | 166 |
1 files changed, 88 insertions, 78 deletions
diff --git a/quartus/dionysos_nios2mmu.qsf b/quartus/dionysos_nios2mmu.qsf index 2aa3d7f..de2936f 100644 --- a/quartus/dionysos_nios2mmu.qsf +++ b/quartus/dionysos_nios2mmu.qsf @@ -54,18 +54,18 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL # Clock inputs # ------------ set_location_assignment PIN_G2 -to clock_50_i -#set_location_assignment PIN_T2 -to et_phy1_tx_clk_1_i -#set_location_assignment PIN_T1 -to et_phy1_rx_clk_1_i +set_location_assignment PIN_T2 -to et_phy1_tx_clk_1_i +set_location_assignment PIN_T1 -to et_phy1_rx_clk_1_i #set_location_assignment PIN_G21 -to usb_clk_i #set_location_assignment PIN_G22 -to sdfe_clk_20mhz_i -#set_location_assignment PIN_T21 -to et_phy2_rx_clk_2_i -#set_location_assignment PIN_T22 -to et_phy2_tx_clk_2_i +set_location_assignment PIN_T21 -to et_phy2_rx_clk_2_i +set_location_assignment PIN_T22 -to et_phy2_tx_clk_2_i set_location_assignment PIN_A12 -to aux_clk_n_i set_location_assignment PIN_B12 -to aux_clk_p_i -#set_location_assignment PIN_AB12 -to et_phy2_rx_clk_1_i -#set_location_assignment PIN_AA12 -to et_phy2_tx_clk_1_i -#set_location_assignment PIN_AB11 -to et_phy1_rx_clk_2_i -#set_location_assignment PIN_AA11 -to et_phy1_tx_clk_2_i +set_location_assignment PIN_AB12 -to et_phy2_rx_clk_1_i +set_location_assignment PIN_AA12 -to et_phy2_tx_clk_1_i +set_location_assignment PIN_AB11 -to et_phy1_rx_clk_2_i +set_location_assignment PIN_AA11 -to et_phy1_tx_clk_2_i # FPGA programming pins # --------------------- @@ -152,32 +152,32 @@ set_location_assignment PIN_J2 -to gp_led_o[3] # FPGA bank 3 # ----------- -#set_location_assignment PIN_V5 -to et_phy1_rx_dv_1_i -#set_location_assignment PIN_U7 -to et_phy1_rx_er_1_i -#set_location_assignment PIN_U8 -to et_phy1_crs_1_i -#set_location_assignment PIN_Y4 -to et_phy1_rxd_1_i[0] -#set_location_assignment PIN_Y3 -to et_phy1_rxd_1_i[1] -#set_location_assignment PIN_Y6 -to et_phy1_rxd_1_i[2] +set_location_assignment PIN_V5 -to et_phy1_rx_dv_1_i +set_location_assignment PIN_U7 -to et_phy1_rx_er_1_i +set_location_assignment PIN_U8 -to et_phy1_crs_1_i +set_location_assignment PIN_Y4 -to et_phy1_rxd_1_i[0] +set_location_assignment PIN_Y3 -to et_phy1_rxd_1_i[1] +set_location_assignment PIN_Y6 -to et_phy1_rxd_1_i[2] #set_location_assignment PIN_AA3 -to ssram_clk_o -set_location_assignment PIN_AB3 -to reserve7_i -#set_location_assignment PIN_W6 -to et_phy1_rxd_1_i[3] -#set_location_assignment PIN_V7 -to et_phy1_col_1_i -#set_location_assignment PIN_AB4 -to et_phy1_tx_en_1_o -#set_location_assignment PIN_AA5 -to et_phy1_txd_1_o[0] -#set_location_assignment PIN_AB5 -to et_phy1_txd_1_o[1] -#set_location_assignment PIN_T8 -to et_phy1_txd_1_o[2] -#set_location_assignment PIN_T9 -to et_phy1_txd_1_o[3] -#set_location_assignment PIN_W7 -to et_phy1_int_1_i -set_location_assignment PIN_Y7 -to reserve2_i -#set_location_assignment PIN_U9 -to et_phy1_rx_dv_2_i -#set_location_assignment PIN_V8 -to et_phy1_rx_er_2_i -#set_location_assignment PIN_W8 -to et_phy1_crs_2_i -#set_location_assignment PIN_AA7 -to et_phy1_rxd_2_i[0] -#set_location_assignment PIN_AB7 -to et_phy1_rxd_2_i[1] -#set_location_assignment PIN_Y8 -to et_phy1_rxd_2_i[2] -#set_location_assignment PIN_T10 -to et_phy1_rxd_2_i[3] -#set_location_assignment PIN_T11 -to et_phy1_col_2_i -set_location_assignment PIN_V9 -to reserve3_i +#set_location_assignment PIN_AB3 -to reserve7_i +set_location_assignment PIN_W6 -to et_phy1_rxd_1_i[3] +set_location_assignment PIN_V7 -to et_phy1_col_1_i +set_location_assignment PIN_AB4 -to et_phy1_tx_en_1_o +set_location_assignment PIN_AA5 -to et_phy1_txd_1_o[0] +set_location_assignment PIN_AB5 -to et_phy1_txd_1_o[1] +set_location_assignment PIN_T8 -to et_phy1_txd_1_o[2] +set_location_assignment PIN_T9 -to et_phy1_txd_1_o[3] +set_location_assignment PIN_W7 -to et_phy1_int_1_i +#set_location_assignment PIN_Y7 -to reserve2_i +set_location_assignment PIN_U9 -to et_phy1_rx_dv_2_i +set_location_assignment PIN_V8 -to et_phy1_rx_er_2_i +set_location_assignment PIN_W8 -to et_phy1_crs_2_i +set_location_assignment PIN_AA7 -to et_phy1_rxd_2_i[0] +set_location_assignment PIN_AB7 -to et_phy1_rxd_2_i[1] +set_location_assignment PIN_Y8 -to et_phy1_rxd_2_i[2] +set_location_assignment PIN_T10 -to et_phy1_rxd_2_i[3] +set_location_assignment PIN_T11 -to et_phy1_col_2_i +#set_location_assignment PIN_V9 -to reserve3_i set_location_assignment PIN_V10 -to et_phy1_tx_en_2_o set_location_assignment PIN_U10 -to et_phy1_txd_2_o[0] set_location_assignment PIN_AA8 -to et_phy1_txd_2_o[1] @@ -186,9 +186,9 @@ set_location_assignment PIN_AA9 -to et_phy1_txd_2_o[3] set_location_assignment PIN_AB9 -to et_phy1_int_2_i set_location_assignment PIN_U11 -to et_phy1_mdc_o set_location_assignment PIN_V11 -to et_phy1_mdio_io -#set_location_assignment PIN_W10 -to rst_et_phy1_n_o -set_location_assignment PIN_Y10 -to gen_led_r_o[3] -set_location_assignment PIN_AA10 -to gen_led_g_o[3] +set_location_assignment PIN_W10 -to rst_et_phy1_n_o +#set_location_assignment PIN_Y10 -to gen_led_r_o[3] +#set_location_assignment PIN_AA10 -to gen_led_g_o[3] # FPGA bank 4 # ----------- @@ -220,42 +220,42 @@ set_location_assignment PIN_AA10 -to gen_led_g_o[3] #set_location_assignment PIN_AA17 -to otg_dreq1_i #set_location_assignment PIN_AB17 -to otg_dack0_n_o #set_location_assignment PIN_AA18 -to otg_dack1_n_o -#set_location_assignment PIN_AB19 -to et_phy2_rx_dv_1_i -set_location_assignment PIN_W17 -to gen_led_r_o[6] -#set_location_assignment PIN_Y17 -to et_phy2_tx_en_1_o -set_location_assignment PIN_AB20 -to gen_led_r_o[2] -set_location_assignment PIN_V16 -to gen_led_g_o[2] -set_location_assignment PIN_U16 -to reserve4_i -set_location_assignment PIN_U17 -to reserve5_i +set_location_assignment PIN_AB19 -to et_phy2_rx_dv_1_i +#set_location_assignment PIN_W17 -to gen_led_r_o[6] +set_location_assignment PIN_Y17 -to et_phy2_tx_en_1_o +#set_location_assignment PIN_AB20 -to gen_led_r_o[2] +#set_location_assignment PIN_V16 -to gen_led_g_o[2] +#set_location_assignment PIN_U16 -to reserve4_i +#set_location_assignment PIN_U17 -to reserve5_i set_location_assignment PIN_T16 -to aux_clk_p_o set_location_assignment PIN_R16 -to aux_clk_n_o -set_location_assignment PIN_R15 -to gen_led_g_o[6] +#set_location_assignment PIN_R15 -to gen_led_g_o[6] # FPGA bank 5 # ----------- -#set_location_assignment PIN_AA22 -to et_phy2_txd_2_o[3] -#set_location_assignment PIN_AA21 -to et_phy2_txd_2_o[2] -#set_location_assignment PIN_T17 -to et_phy2_txd_2_o[1] -#set_location_assignment PIN_T18 -to et_phy2_txd_2_o[0] -#set_location_assignment PIN_W20 -to et_phy2_txd_1_o[3] -#set_location_assignment PIN_W19 -to et_phy2_txd_1_o[2] -#set_location_assignment PIN_Y22 -to et_phy2_txd_1_o[1] -#set_location_assignment PIN_Y21 -to et_phy2_txd_1_o[0] -#set_location_assignment PIN_U20 -to et_phy2_rxd_2_i[3] -#set_location_assignment PIN_U19 -to et_phy2_rxd_2_i[2] -#set_location_assignment PIN_W22 -to et_phy2_rxd_2_i[1] -#set_location_assignment PIN_W21 -to et_phy2_rxd_2_i[0] -#set_location_assignment PIN_P15 -to et_phy2_rxd_1_i[3] -#set_location_assignment PIN_P16 -to et_phy2_rxd_1_i[2] -#set_location_assignment PIN_R17 -to et_phy2_rxd_1_i[1] -#set_location_assignment PIN_P17 -to et_phy2_rxd_1_i[0] -#set_location_assignment PIN_V22 -to et_phy2_rx_er_1_i -#set_location_assignment PIN_V21 -to et_phy2_crs_2_i -#set_location_assignment PIN_R20 -to rst_et_phy2_n_o -#set_location_assignment PIN_U22 -to et_phy2_rx_er_2_i -#set_location_assignment PIN_U21 -to et_phy2_col_2_i -#set_location_assignment PIN_R18 -to et_phy2_crs_1_i -#set_location_assignment PIN_R19 -to et_phy2_col_1_i +set_location_assignment PIN_AA22 -to et_phy2_txd_2_o[3] +set_location_assignment PIN_AA21 -to et_phy2_txd_2_o[2] +set_location_assignment PIN_T17 -to et_phy2_txd_2_o[1] +set_location_assignment PIN_T18 -to et_phy2_txd_2_o[0] +set_location_assignment PIN_W20 -to et_phy2_txd_1_o[3] +set_location_assignment PIN_W19 -to et_phy2_txd_1_o[2] +set_location_assignment PIN_Y22 -to et_phy2_txd_1_o[1] +set_location_assignment PIN_Y21 -to et_phy2_txd_1_o[0] +set_location_assignment PIN_U20 -to et_phy2_rxd_2_i[3] +set_location_assignment PIN_U19 -to et_phy2_rxd_2_i[2] +set_location_assignment PIN_W22 -to et_phy2_rxd_2_i[1] +set_location_assignment PIN_W21 -to et_phy2_rxd_2_i[0] +set_location_assignment PIN_P15 -to et_phy2_rxd_1_i[3] +set_location_assignment PIN_P16 -to et_phy2_rxd_1_i[2] +set_location_assignment PIN_R17 -to et_phy2_rxd_1_i[1] +set_location_assignment PIN_P17 -to et_phy2_rxd_1_i[0] +set_location_assignment PIN_V22 -to et_phy2_rx_er_1_i +set_location_assignment PIN_V21 -to et_phy2_crs_2_i +set_location_assignment PIN_R20 -to rst_et_phy2_n_o +set_location_assignment PIN_U22 -to et_phy2_rx_er_2_i +set_location_assignment PIN_U21 -to et_phy2_col_2_i +set_location_assignment PIN_R18 -to et_phy2_crs_1_i +set_location_assignment PIN_R19 -to et_phy2_col_1_i #set_location_assignment PIN_N16 -to mpd_io[0] #set_location_assignment PIN_R22 -to mpd_io[1] #set_location_assignment PIN_R21 -to mpd_io[2] @@ -266,12 +266,12 @@ set_location_assignment PIN_R15 -to gen_led_g_o[6] #set_location_assignment PIN_N19 -to mpd_io[7] set_location_assignment PIN_N18 -to reserve6_i set_location_assignment PIN_N21 -to fpga_reset_n_i -#set_location_assignment PIN_M22 -to et_phy2_rx_dv_2_i -#set_location_assignment PIN_M21 -to et_phy2_tx_en_2_o -#set_location_assignment PIN_AA20 -to et_phy2_int_1_i -#set_location_assignment PIN_M20 -to et_phy2_int_2_i -#set_location_assignment PIN_M19 -to et_phy2_mdc_o -#set_location_assignment PIN_M16 -to et_phy2_mdio_io +set_location_assignment PIN_M22 -to et_phy2_rx_dv_2_i +set_location_assignment PIN_M21 -to et_phy2_tx_en_2_o +set_location_assignment PIN_AA20 -to et_phy2_int_1_i +set_location_assignment PIN_M20 -to et_phy2_int_2_i +set_location_assignment PIN_M19 -to et_phy2_mdc_o +set_location_assignment PIN_M16 -to et_phy2_mdio_io # FPGA bank 6 # ----------- @@ -364,7 +364,7 @@ set_location_assignment PIN_F11 -to dram_a_o[12] #set_location_assignment PIN_C10 -to sdfe_aux_0_4_i #set_location_assignment PIN_G11 -to sdfe_aux_0_5_i #set_location_assignment PIN_A8 -to sdfe_refclk_0_i -set_location_assignment PIN_B8 -to reserve8_i +#set_location_assignment PIN_B8 -to reserve8_i #set_location_assignment PIN_B7 -to sdfe_dout_3_i #set_location_assignment PIN_A6 -to sdfe_din_3_o #set_location_assignment PIN_B6 -to sdfe_aux_3_0_o @@ -374,8 +374,8 @@ set_location_assignment PIN_B8 -to reserve8_i #set_location_assignment PIN_H11 -to sdfe_aux_3_4_i #set_location_assignment PIN_H10 -to sdfe_aux_3_5_i #set_location_assignment PIN_A5 -to sdfe_refclk_3_i -set_location_assignment PIN_B5 -to gen_led_r_o[1] -set_location_assignment PIN_G10 -to gen_led_g_o[1] +#set_location_assignment PIN_B5 -to gen_led_r_o[1] +#set_location_assignment PIN_G10 -to gen_led_g_o[1] #set_location_assignment PIN_F10 -to sdfe_scdi_o #set_location_assignment PIN_C6 -to sdfe_scdo_i #set_location_assignment PIN_D7 -to sdfe_scck_o @@ -392,7 +392,7 @@ set_location_assignment PIN_G10 -to gen_led_g_o[1] #set_location_assignment PIN_F7 -to mpad_o[2] #set_location_assignment PIN_G7 -to mpad_o[3] #set_location_assignment PIN_F9 -to mpad_o[4] -#set_location_assignment PIN_E5 -to et_phy_clk_50mhz_o +set_location_assignment PIN_E5 -to et_phy_clk_50mhz_o # EDA Netlist Writer Assignments # ============================== @@ -429,6 +429,17 @@ set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + + + + +set_global_assignment -name VHDL_FILE ../lib/ethernet/components/rmii_phy_to_mii_mac.vhd +set_global_assignment -name VHDL_FILE ../lib/misc/components/bibuf_async.vhd +set_global_assignment -name VHDL_FILE ../lib/misc/ines_vhdl_lib_base_pkg.vhd +set_global_assignment -name VHDL_FILE ../lib/misc/reduce_pkg.vhd +set_global_assignment -name VHDL_FILE ../lib/ethernet/components/mii_management_transmit.vhd +set_global_assignment -name VHDL_FILE ../lib/ethernet/components/mdio_interface.vhd +set_global_assignment -name VHDL_FILE ../lib/ethernet/components/rmii_in_out.vhd set_global_assignment -name QIP_FILE ../lib/altera/sinet_pll.qip set_global_assignment -name VHDL_FILE ../lib/misc/components/reset_sync.vhd set_global_assignment -name VHDL_FILE ../dionysos_top.vhd @@ -436,5 +447,4 @@ set_global_assignment -name QIP_FILE dionysos_nios2mmu.qip set_global_assignment -name VHDL_FILE dionysos_nios2mmu.vhd set_global_assignment -name SDC_FILE dionysos_nios2mmu.sdc - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file |