diff options
Diffstat (limited to 'quartus/dionysos_nios2mmu.sdc')
-rw-r--r-- | quartus/dionysos_nios2mmu.sdc | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/quartus/dionysos_nios2mmu.sdc b/quartus/dionysos_nios2mmu.sdc index a4948ef..dab2e78 100644 --- a/quartus/dionysos_nios2mmu.sdc +++ b/quartus/dionysos_nios2mmu.sdc @@ -27,6 +27,18 @@ create_clock -name epcs_rd_clk -period 20MHz -add [get_ports config_dclk_o] # Create Generated Clock (Used for Clock relations (PLL)) #************************************************************** +# connected via PLL (Normal Mode) +create_generated_clock -name pll_1_clk_0 -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \ + [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[0]}] + +# connected via PLL (Normal Mode, Divided by 2) +create_generated_clock -name pll_1_clk_1 -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \ + -divide_by 2 [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[1]}] + +# connected via PLL (Normal Mode, Divided by 4) +create_generated_clock -name pll_1_clk_2 -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \ + -divide_by 4 [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[2]}] + # connected via PLL (Normal Mode, -3ns phase shift create_generated_clock -name pll_1_clk_3 -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \ -phase -54.000 [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[3]}] @@ -39,7 +51,6 @@ create_generated_clock -name clock_dram -source [get_pins {sinet_pll|alt # Set Clock Groups #************************************************************** - # EPCS16N-98364 (EPCS): cut all paths between the write and read clock (just one of both is active at any time) set_clock_groups -asynchronous -group [get_clocks epcs_wd_clk] -group [get_clocks epcs_rd_clk] -group [get_clocks {pll_1_clk_0}] |