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Diffstat (limited to 'quartus/dionysos_nios2mmu.sopc')
-rw-r--r--quartus/dionysos_nios2mmu.sopc257
1 files changed, 203 insertions, 54 deletions
diff --git a/quartus/dionysos_nios2mmu.sopc b/quartus/dionysos_nios2mmu.sopc
index 1fc4c41..3ceafcf 100644
--- a/quartus/dionysos_nios2mmu.sopc
+++ b/quartus/dionysos_nios2mmu.sopc
@@ -4,6 +4,11 @@
{
element jtag_uart_0.avalon_jtag_slave
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
value = "41953472";
@@ -14,7 +19,7 @@
{
datum _sortIndex
{
- value = "5";
+ value = "6";
type = "int";
}
datum megawizard_uipreferences
@@ -31,14 +36,32 @@
type = "int";
}
}
- element triple_speed_ethernet_0.control_port
+ element tse_mac.control_port
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
value = "41952256";
type = "long";
}
}
+ element sysid.control_slave
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4759552";
+ type = "long";
+ }
+ }
element cpu_0
{
datum _sortIndex
@@ -48,23 +71,33 @@
}
datum megawizard_uipreferences
{
- value = "{}";
+ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}";
type = "String";
}
}
- element sgdma_tx.csr
+ element sgdma_rx.csr
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "41953344";
+ value = "41953280";
type = "long";
}
}
- element sgdma_rx.csr
+ element sgdma_tx.csr
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "41953280";
+ value = "41953344";
type = "long";
}
}
@@ -72,7 +105,7 @@
{
datum _sortIndex
{
- value = "13";
+ value = "14";
type = "int";
}
datum megawizard_uipreferences
@@ -86,6 +119,11 @@
}
element epcs_flash_controller_0.epcs_control_port
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
value = "41949184";
@@ -96,7 +134,7 @@
{
datum _sortIndex
{
- value = "7";
+ value = "8";
type = "int";
}
datum megawizard_uipreferences
@@ -107,6 +145,11 @@
}
element cpu_0.jtag_debug_module
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
value = "41947136";
@@ -117,7 +160,7 @@
{
datum _sortIndex
{
- value = "9";
+ value = "10";
type = "int";
}
datum megawizard_uipreferences
@@ -130,7 +173,7 @@
{
datum _sortIndex
{
- value = "2";
+ value = "3";
type = "int";
}
datum megawizard_uipreferences
@@ -139,61 +182,104 @@
type = "String";
}
}
- element cfi_flash_0.s1
+ element onchip_memory2_0.s1
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "37748736";
+ value = "41951232";
type = "long";
}
}
- element uart_0.s1
+ element descriptor_memory.s1
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "41953440";
+ value = "75759616";
type = "long";
}
}
- element descriptor_memory.s1
+ element sdram_0.s1
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "0";
+ value = "16777216";
type = "long";
}
}
- element onchip_memory2_0.s1
+ element timer_0.s1
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "41951232";
+ value = "41953408";
type = "long";
}
}
- element timer_0.s1
+ element watchdog_timer.s1
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "41953408";
+ value = "76021760";
type = "long";
}
}
- element sdram_0.s1
+ element cfi_flash_0.s1
{
datum _lockedAddress
{
- value = "0";
+ value = "1";
type = "boolean";
}
datum baseAddress
{
- value = "16777216";
+ value = "37748736";
+ type = "long";
+ }
+ }
+ element uart_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "41953440";
type = "long";
}
}
element onchip_memory2_0.s2
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
value = "41951232";
@@ -204,7 +290,7 @@
{
datum _sortIndex
{
- value = "3";
+ value = "4";
type = "int";
}
datum megawizard_uipreferences
@@ -217,12 +303,12 @@
{
datum _sortIndex
{
- value = "11";
+ value = "12";
type = "int";
}
datum megawizard_uipreferences
{
- value = "{}";
+ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}";
type = "String";
}
}
@@ -230,7 +316,20 @@
{
datum _sortIndex
{
- value = "12";
+ value = "13";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}";
+ type = "String";
+ }
+ }
+ element sysid
+ {
+ datum _sortIndex
+ {
+ value = "2";
type = "int";
}
datum megawizard_uipreferences
@@ -243,12 +342,12 @@
{
datum _sortIndex
{
- value = "6";
+ value = "7";
type = "int";
}
datum megawizard_uipreferences
{
- value = "{}";
+ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}";
type = "String";
}
}
@@ -256,7 +355,7 @@
{
datum _sortIndex
{
- value = "4";
+ value = "5";
type = "int";
}
datum megawizard_uipreferences
@@ -265,16 +364,16 @@
type = "String";
}
}
- element triple_speed_ethernet_0
+ element tse_mac
{
datum _sortIndex
{
- value = "10";
+ value = "11";
type = "int";
}
datum megawizard_uipreferences
{
- value = "{}";
+ value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}";
type = "String";
}
}
@@ -282,7 +381,20 @@
{
datum _sortIndex
{
- value = "8";
+ value = "9";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element watchdog_timer
+ {
+ datum _sortIndex
+ {
+ value = "15";
type = "int";
}
datum megawizard_uipreferences
@@ -298,8 +410,8 @@
<parameter name="hardcopyCompatible" value="false" />
<parameter name="hdlLanguage" value="VHDL" />
<parameter name="projectName">dionysos_nios2mmu.qpf</parameter>
- <parameter name="systemHash" value="-62283505486" />
- <parameter name="timeStamp" value="1280742475274" />
+ <parameter name="systemHash" value="-77315762035" />
+ <parameter name="timeStamp" value="1295440989718" />
<module name="clk_0" kind="clock_source" version="9.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
@@ -336,7 +448,7 @@
<parameter name="setting_activateModelChecker" value="false" />
<parameter name="setting_HDLSimCachesCleared" value="true" />
<parameter name="setting_HBreakTest" value="false" />
- <parameter name="resetSlave" value="cfi_flash_0.s1" />
+ <parameter name="resetSlave" value="sdram_0.s1" />
<parameter name="resetOffset" value="0" />
<parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
<parameter name="muldiv_divider" value="true" />
@@ -501,11 +613,7 @@
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
- <module
- name="triple_speed_ethernet_0"
- kind="triple_speed_ethernet"
- version="9.1"
- enabled="1">
+ <module name="tse_mac" kind="triple_speed_ethernet" version="9.1" enabled="1">
<parameter name="atlanticSinkClockRate" value="0" />
<parameter name="atlanticSinkClockSource" value="unassigned" />
<parameter name="atlanticSourceClockRate" value="0" />
@@ -622,6 +730,22 @@
<parameter name="transferMode" value="MEMORY_TO_STREAM" />
<parameter name="writeBurstcountWidth" value="4" />
</module>
+ <module
+ name="watchdog_timer"
+ kind="altera_avalon_timer"
+ version="9.1"
+ enabled="1">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="10" />
+ <parameter name="periodUnits" value="SEC" />
+ <parameter name="resetOutput" value="true" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset" value="WATCHDOG" />
+ </module>
+ <module name="sysid" kind="altera_avalon_sysid" version="9.1" enabled="1" />
<connection kind="clock" version="9.1" start="clk_0.clk" end="cpu_0.clk" />
<connection
kind="avalon"
@@ -780,17 +904,17 @@
kind="clock"
version="9.1"
start="clk_0.clk"
- end="triple_speed_ethernet_0.receive_clock_connection" />
+ end="tse_mac.receive_clock_connection" />
<connection
kind="clock"
version="9.1"
start="clk_0.clk"
- end="triple_speed_ethernet_0.transmit_clock_connection" />
+ end="tse_mac.transmit_clock_connection" />
<connection
kind="avalon"
version="6.1"
start="cpu_0.data_master"
- end="triple_speed_ethernet_0.control_port">
+ end="tse_mac.control_port">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x02802400" />
</connection>
@@ -798,7 +922,7 @@
kind="clock"
version="9.1"
start="clk_0.clk"
- end="triple_speed_ethernet_0.control_port_clock_connection" />
+ end="tse_mac.control_port_clock_connection" />
<connection kind="clock" version="9.1" start="clk_0.clk" end="sgdma_rx.clk" />
<connection
kind="avalon"
@@ -842,7 +966,7 @@
start="sgdma_rx.descriptor_read"
end="descriptor_memory.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
+ <parameter name="baseAddress" value="0x04840000" />
</connection>
<connection
kind="avalon"
@@ -850,7 +974,7 @@
start="sgdma_rx.descriptor_write"
end="descriptor_memory.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
+ <parameter name="baseAddress" value="0x04840000" />
</connection>
<connection kind="avalon" version="6.1" start="sgdma_rx.m_write" end="sdram_0.s1">
<parameter name="arbitrationPriority" value="1" />
@@ -859,13 +983,13 @@
<connection
kind="avalon_streaming"
version="9.1"
- start="triple_speed_ethernet_0.receive"
+ start="tse_mac.receive"
end="sgdma_rx.in" />
<connection
kind="avalon_streaming"
version="9.1"
start="sgdma_tx.out"
- end="triple_speed_ethernet_0.transmit" />
+ end="tse_mac.transmit" />
<connection kind="avalon" version="6.1" start="sgdma_tx.m_read" end="sdram_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x01000000" />
@@ -876,7 +1000,7 @@
start="sgdma_tx.descriptor_read"
end="descriptor_memory.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
+ <parameter name="baseAddress" value="0x04840000" />
</connection>
<connection
kind="avalon"
@@ -884,7 +1008,7 @@
start="sgdma_tx.descriptor_write"
end="descriptor_memory.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
+ <parameter name="baseAddress" value="0x04840000" />
</connection>
<connection
kind="avalon"
@@ -892,6 +1016,31 @@
start="cpu_0.data_master"
end="descriptor_memory.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0000" />
+ <parameter name="baseAddress" value="0x04840000" />
+ </connection>
+ <connection kind="clock" version="9.1" start="clk_0.clk" end="watchdog_timer.clk" />
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="watchdog_timer.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x04880000" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="9.1"
+ start="cpu_0.d_irq"
+ end="watchdog_timer.irq">
+ <parameter name="irqNumber" value="6" />
+ </connection>
+ <connection kind="clock" version="9.1" start="clk_0.clk" end="sysid.clk" />
+ <connection
+ kind="avalon"
+ version="6.1"
+ start="cpu_0.data_master"
+ end="sysid.control_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0048a000" />
</connection>
</system>
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-22 07:07:01 +0000