From 0fffe741a1f1da87645e2833d06bc0851e6ff28e Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 18 Jun 2010 11:53:45 +0200 Subject: Add TSE MAC and hook it up (code taken from SInet) --- dionysos_top.vhd | 318 +- quartus/dionysos_nios2mmu.bsf | 295 +- quartus/dionysos_nios2mmu.qsf | 166 +- quartus/dionysos_nios2mmu.sopc | 345 +- quartus/dionysos_nios2mmu.sopcinfo | 7248 ++++++++++++++++++++++++++++++++++-- 5 files changed, 7809 insertions(+), 563 deletions(-) diff --git a/dionysos_top.vhd b/dionysos_top.vhd index 208b967..66e0392 100644 --- a/dionysos_top.vhd +++ b/dionysos_top.vhd @@ -24,6 +24,10 @@ library ieee; use ieee.numeric_std.all; library ines_misc; use ines_misc.reset_sync_pkg.all; + use ines_misc.bibuf_async_pkg.all; +library ines_ethernet; + use ines_ethernet.rmii_in_out_pkg.all; + use ines_ethernet.mdio_interface_pkg.all; --! \brief Top file for design on Dionysos board entity dionysos_top is @@ -103,8 +107,91 @@ entity dionysos_top is flash_reset_n_o : out std_logic; --! FLASH Reset flash_oe_n_o : out std_logic; --! FLASH Output Enable flash_ce_n_o : out std_logic; --! FLASH Chip Enable - fash_acc_o : out std_logic --! + fash_acc_o : out std_logic; --! --@} + + --!@name 100BaseTX Phy0 & Phy1 50 MHz Clock output + --@{ + --! \anchor phy11_grp + et_phy_clk_50mhz_o : out std_logic; --! PHY clock for all RMII ethernet phys + et_phy1_tx_clk_1_i : in std_logic; --! PHY clock in MII mode (not used in RMII mode) + et_phy1_rx_clk_1_i : in std_logic; --! PHY clock in MII mode (not used in RMII mode) + et_phy2_rx_clk_2_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) + et_phy2_tx_clk_2_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) + et_phy2_rx_clk_1_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) + et_phy2_tx_clk_1_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) + et_phy1_rx_clk_2_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) + et_phy1_tx_clk_2_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) + --@} + + --!@name 100BaseTX Phy1 Port 1 + --@{ + --! \anchor phy11_grp + et_phy1_rxd_1_i : in std_logic_vector(3 downto 0); --! Dual eth phy1: phy1 receive data + et_phy1_rx_dv_1_i : in std_logic; --! Dual eth phy1: phy1 rx data valid + et_phy1_crs_1_i : in std_logic; --! Dual eth phy1: phy1 carrier sense + et_phy1_col_1_i : in std_logic; --! Dual eth phy1: phy1 collision detect + et_phy1_txd_1_o : out std_logic_vector(3 downto 0); --! Dual eth phy1: phy1 transmit data + et_phy1_tx_en_1_o : out std_logic; --! Dual eth phy1: phy1 tx enable + et_phy1_int_1_i : in std_logic; --! Dual eth phy1: phy1 interrupt/power down (not used) + et_phy1_rx_er_1_i : in std_logic; --! Dual eth phy1: phy1 error (not used) + --@} + + --!@name 100BaseTX Phy1 Port 2 + --@{ + --! \anchor phy12_grp + et_phy1_rxd_2_i : in std_logic_vector(3 downto 0); --! Dual eth phy1: phy2 receive data + et_phy1_rx_dv_2_i : in std_logic; --! Dual eth phy1: phy2 rx data valid + et_phy1_crs_2_i : in std_logic; --! Dual eth phy1: phy2 carrier sense + et_phy1_col_2_i : in std_logic; --! Dual eth phy1: phy2 collision detect + et_phy1_txd_2_o : out std_logic_vector(3 downto 0); --! Dual eth phy1: phy2 transmit data + et_phy1_tx_en_2_o : out std_logic; --! Dual eth phy1: phy2 tx enable + et_phy1_int_2_i : in std_logic; --! Dual eth phy1: phy2 interrupt/power down (not used) + et_phy1_rx_er_2_i : in std_logic; --! Dual eth phy1: phy2 error (not used) + --@} + + --!@name 100BaseTX Phy2 Port 1 + --@{ + --! \anchor phy11_grp + et_phy2_rxd_1_i : in std_logic_vector(3 downto 0); --! Dual eth phy1: phy1 receive data + et_phy2_rx_dv_1_i : in std_logic; --! Dual eth phy1: phy1 rx data valid + et_phy2_crs_1_i : in std_logic; --! Dual eth phy1: phy1 carrier sense + et_phy2_col_1_i : in std_logic; --! Dual eth phy1: phy1 collision detect + et_phy2_txd_1_o : out std_logic_vector(3 downto 0); --! Dual eth phy1: phy1 transmit data + et_phy2_tx_en_1_o : out std_logic; --! Dual eth phy1: phy1 tx enable + et_phy2_int_1_i : in std_logic; --! Dual eth phy1: phy1 interrupt/power down (not used) + et_phy2_rx_er_1_i : in std_logic; --! Dual eth phy1: phy1 error (not used) + --@} + + --!@name 100BaseTX Phy2 Port 2 + --@{ + --! \anchor phy12_grp + et_phy2_rxd_2_i : in std_logic_vector(3 downto 0); --! Dual eth phy1: phy2 receive data + et_phy2_rx_dv_2_i : in std_logic; --! Dual eth phy1: phy2 rx data valid + et_phy2_crs_2_i : in std_logic; --! Dual eth phy1: phy2 carrier sense + et_phy2_col_2_i : in std_logic; --! Dual eth phy1: phy2 collision detect + et_phy2_txd_2_o : out std_logic_vector(3 downto 0); --! Dual eth phy1: phy2 transmit data + et_phy2_tx_en_2_o : out std_logic; --! Dual eth phy1: phy2 tx enable + et_phy2_int_2_i : in std_logic; --! Dual eth phy1: phy2 interrupt/power down (not used) + et_phy2_rx_er_2_i : in std_logic; --! Dual eth phy1: phy2 error (not used) + --@} + + --!@name Phy 1 configuration (MDIO, reset) + --@{ + --! \anchor mdio_grp + et_phy1_mdc_o : out std_logic; --! Dual eth phy1, phy2 Management clock + et_phy1_mdio_io : inout std_logic; --! Dual eth phy1, phy2 data + rst_et_phy1_n_o : out std_logic; --! Ethernet phy reset + --@} + + --!@name Phy 2 configuration (MDIO, reset) + --@{ + --! \anchor mdio_grp + et_phy2_mdc_o : out std_logic; --! Dual eth phy1, phy2 Management clock + et_phy2_mdio_io : inout std_logic; --! Dual eth phy1, phy2 data + rst_et_phy2_n_o : out std_logic --! Ethernet phy reset + --@} + ); end dionysos_top; @@ -118,11 +205,13 @@ architecture rtl of dionysos_top is --! 25 MHz Clock signal pll_clk_25 : std_logic; --! 12.5 MHz Clock - signal pll_clk_12_5 : std_logic; + signal pll_clk_12_5 : std_logic; --! main design reset after reset circuit signal reset_n : std_logic; --! synchronous reset signal fpga_reset_n_ff : std_logic; + --! synchronous reset + signal fpga_reset_n_ff_100 : std_logic; --! Reset for the NIOS. Active in Ethernet Modus (no DSL) signal reset_nios_n : std_logic; @@ -137,9 +226,79 @@ architecture rtl of dionysos_top is signal dram_ba : std_logic_vector(1 downto 0); --@} + --! @name RX byte stream interface of ethernet phy 1 + --! (see \subpage bs_interface_stb) + --@{ + --! Ethernet phy 1 RMII receive data + signal et_phy1_rx_data_1 : std_logic_vector(7 downto 0); + signal et_phy1_rx_data_2 : std_logic_vector(7 downto 0); + --! Ethernet phy 1 RMII receive strobe + signal et_phy1_rx_stb_1 : std_logic; + signal et_phy1_rx_stb_2 : std_logic; + --! Ethernet phy 1 RMII receive data valid + signal et_phy1_rx_dv_1 : std_logic; + signal et_phy1_rx_dv_2 : std_logic; + --@} + + --! \page bs_interface_stb Bytestream Interface (Strobe) + --! \image html timingdiagramme_bytestream_interface_stb.png "bytestream interface with strobe signal" + + --! @name RX interface 2 of ethernet phy 2 + --@{ + --! Ethernet phy 2 port 2 RMII receive data + signal et_phy2_rx_data_2 : std_logic_vector(7 downto 0); + --! Ethernet phy 2 port 2 RMII receive strobe + signal et_phy2_rx_stb_2 : std_logic; + --! Ethernet phy 2 port 2 RMII receive data valid + signal et_phy2_rx_dv_2 : std_logic; + --@} + + --! @name TX interface 2 of ethernet phy 2 + --@{ + --! Ethernet phy 2 port 2 RMII transmit data + signal et_phy2_txd_2 : std_logic_vector(7 downto 0); + --! Ethernet phy 2 port 2 RMII transmit eanble + signal et_phy2_tx_en_2 : std_logic; + --! Ethernet phy 2 port 2 RMII transmit data acknowledge + signal et_phy2_tx_ack_2 : std_logic; + --@} + + --! link status of ethernet interfaces (from MDIO) \todo tidy mdio + signal et_phy1_link_status : std_logic_vector(3 downto 0); + --! synchronised on clock dip switch states signal sw_sync : std_logic_vector(switch_i'range); + --! @name MDIO signals (100BaseTX phy configuration interface) + --@{ + --! output enable for mdio data + signal et_phy1_mdio_oe : std_logic; + signal et_phy2_mdio_oe : std_logic; + --! mdio data input + signal et_phy1_mdio_in : std_logic; + signal et_phy2_mdio_in : std_logic; + --! mdio data output + signal et_phy1_mdio_out : std_logic; + signal et_phy2_mdio_out : std_logic; + --@} + + --! @name Signals between TSE mac (MII mode) and RMII bridge + --@{ + signal mii_txd_from_mac_0 : std_logic_vector(3 downto 0); + signal mii_rx_dv_to_mac_0 : std_logic; + signal mii_rxd_to_mac_0 : std_logic_vector(3 downto 0); + signal mii_tx_en_from_mac_0 : std_logic; + signal mii_txd_from_mac_1 : std_logic_vector(3 downto 0); + signal mii_rx_dv_to_mac_1 : std_logic; + signal mii_rxd_to_mac_1 : std_logic_vector(3 downto 0); + signal mii_tx_en_from_mac_1 : std_logic; + + signal mac_mdio_in : std_logic; + signal mac_mdio_out : std_logic; + signal mac_mdio_en : std_logic; + signal mac_mdio_en_n : std_logic; + --@} + begin --! @name Components --@{ @@ -156,6 +315,9 @@ architecture rtl of dionysos_top is c3 => dram_clk_o -- 50MHz clock output (-3ns) ); + -- generate ETH-PHY 50MHz clock + et_phy_clk_50mhz_o <= pll_clk_50; + --! synchronize reset reset_n_sync : reset_sync generic map( @@ -167,6 +329,8 @@ architecture rtl of dionysos_top is reset2_n_i => '1', reset_n_o => fpga_reset_n_ff ); + rst_et_phy1_n_o <= fpga_reset_n_ff; -- reset for de RMII-PHY 0 + rst_et_phy2_n_o <= fpga_reset_n_ff_100; -- reset for de RMII-PHY 1 --! Delay reset => Latch in Time from Power up for the RMII-Phy (min 167ms) reset_gen : reset_sync @@ -180,6 +344,18 @@ architecture rtl of dionysos_top is reset_n_o => reset_n -- reset for all other components ); + --! Delay reset for PHY Nr. 2 => so that the two phy's aren't exactly synchron + reset_gen_100 : reset_sync + generic map( + STAGES => 100 --2us + ) + port map( + clk_i => pll_clk_50, + reset1_n_i => fpga_reset_n_ff, + reset2_n_i => '1', + reset_n_o => fpga_reset_n_ff_100 -- reset 100 clocks delayed + ); + -- NIOSII CPU flash_reset_n_o <= '1'; fash_acc_o <= '0'; -- Hardware Write Protect input (accelerated program operations) @@ -229,7 +405,143 @@ architecture rtl of dionysos_top is data0_to_the_epcs_flash_controller_0 => config_data0_i, dclk_from_the_epcs_flash_controller_0 => config_dclk_o, sce_from_the_epcs_flash_controller_0 => config_ce_n_o, - sdo_from_the_epcs_flash_controller_0 => config_asd0_o + sdo_from_the_epcs_flash_controller_0 => config_asd0_o, + + -- TSE MAC + -- ena_10_from_the_triple_speed_ethernet_0 => ena_10_from_the_triple_speed_ethernet_0, + -- eth_mode_from_the_triple_speed_ethernet_0 => eth_mode_from_the_triple_speed_ethernet_0, + gm_rx_d_to_the_triple_speed_ethernet_0 => (others => '0'), + gm_rx_dv_to_the_triple_speed_ethernet_0 => '0', + gm_rx_err_to_the_triple_speed_ethernet_0 => '0', + -- gm_tx_d_from_the_triple_speed_ethernet_0 => gm_tx_d_from_the_triple_speed_ethernet_0, + -- gm_tx_en_from_the_triple_speed_ethernet_0 => gm_tx_en_from_the_triple_speed_ethernet_0, + -- gm_tx_err_from_the_triple_speed_ethernet_0 => gm_tx_err_from_the_triple_speed_ethernet_0, + m_rx_col_to_the_triple_speed_ethernet_0 => et_phy2_col_1_i, + m_rx_crs_to_the_triple_speed_ethernet_0 => '1', -- et_phy2_crs_1_i is not the same in rmii mode + m_rx_d_to_the_triple_speed_ethernet_0 => mii_rxd_to_mac_0, + m_rx_en_to_the_triple_speed_ethernet_0 => mii_rx_dv_to_mac_0, + m_rx_err_to_the_triple_speed_ethernet_0 => '0', + mdio_in_to_the_triple_speed_ethernet_0 => mac_mdio_in, + m_tx_d_from_the_triple_speed_ethernet_0 => mii_txd_from_mac_0, + m_tx_en_from_the_triple_speed_ethernet_0 => mii_tx_en_from_mac_0, + -- m_tx_err_from_the_triple_speed_ethernet_0 => m_tx_err_from_the_triple_speed_ethernet_0, + mdc_from_the_triple_speed_ethernet_0 => et_phy2_mdc_o, + mdio_oen_from_the_triple_speed_ethernet_0 => mac_mdio_en_n, + mdio_out_from_the_triple_speed_ethernet_0 => mac_mdio_out, + rx_clk_to_the_triple_speed_ethernet_0 => pll_clk_25, + set_1000_to_the_triple_speed_ethernet_0 => '0', -- tie to 0 if not used + set_10_to_the_triple_speed_ethernet_0 => '0', -- tie to 0 if not used + tx_clk_to_the_triple_speed_ethernet_0 => pll_clk_25 + ); + + --------------------------------------------------------------------- + -- ethernet MDIO for connection between TSE and PHY 2 + --------------------------------------------------------------------- + + --! MDIO bidirectional data buffer + mdio_phy_2_data_buf : bibuf_async + port map( + oe => mac_mdio_en, + io => et_phy2_mdio_io, + inp => mac_mdio_out, + outp => mac_mdio_in ); + mac_mdio_en <= not mac_mdio_en_n; + + ------------------------------------------------------------------------ + -- Converts the rmii interface to the mii interface + ------------------------------------------------------------------------ + + et_phy2_txd_1_o(3 downto 2) <= "00"; + + rmii_phy_to_mii_mac_0 : entity ines_ethernet.rmii_phy_to_mii_mac + port map( + reset_n_i => reset_n, + clk_25_i => pll_clk_25, + clk_50_i => pll_clk_50, + rmii_crs_i => et_phy2_crs_1_i, + + -- Transmit Path + mii_tx_en_i => mii_tx_en_from_mac_0, + mii_txd_i => mii_txd_from_mac_0, + rmii_tx_en_o => et_phy2_tx_en_1_o, + rmii_txd_o => et_phy2_txd_1_o(1 downto 0), + + -- Receive Path + rmii_rx_dv_i => et_phy2_rx_dv_1_i, + rmii_rxd_i => et_phy2_rxd_1_i(1 downto 0), + + mii_rx_dv_o => mii_rx_dv_to_mac_0, + mii_rxd_o => mii_rxd_to_mac_0 + ); + + et_phy2_txd_2_o(3 downto 2) <= "00"; + + rmii_phy_to_mii_mac_1 : entity ines_ethernet.rmii_phy_to_mii_mac + port map( + reset_n_i => reset_n, + clk_25_i => pll_clk_25, + clk_50_i => pll_clk_50, + rmii_crs_i => et_phy2_crs_2_i, + + -- Transmit Path + mii_tx_en_i => mii_tx_en_from_mac_1, + mii_txd_i => mii_txd_from_mac_1, + rmii_tx_en_o => et_phy2_tx_en_2_o, + rmii_txd_o => et_phy2_txd_2_o(1 downto 0), + + -- Receive Path + rmii_rx_dv_i => et_phy2_rx_dv_2_i, + rmii_rxd_i => et_phy2_rxd_2_i(1 downto 0), + + mii_rx_dv_o => mii_rx_dv_to_mac_1, + mii_rxd_o => mii_rxd_to_mac_1 + ); + + ------------------------------------------------------------------------ + -- MDIO Interface + ------------------------------------------------------------------------ + --! MDIO interface for ethernet phy configuration + mdio : entity ines_ethernet.mdio_interface + generic map( + C_SET_TO_MII => false, + CLK_DIVIDER => 10, -- divider for MDC + CHK_INTERVAL => 50e6, -- link check interval in clk_i cycles +-- CHK_INTERVAL => 500, -- for Testbench + NO_OF_PORTS => 2, -- number of ports to poll => max 4 + ADDR_PORT_1 => 0, + ADDR_PORT_2 => 1, + ADDR_PORT_3 => 2, + ADDR_PORT_4 => 3) + port map( + clk_i => pll_clk_50, + reset_n_i => reset_n, + -- manual access (could be connected to the CPU interface...) + phy_addr_i => (others => '0'), + phy_reg_i => (others => '0'), + phy_data_i => (others => '0'), + phy_data_o => open, + send_i => '0', + read_i => '0', + busy_n_o => open, + -- Status out + link_o => et_phy1_link_status, -- 1= link OK + reset_phy_i => (others => '0'), -- 1= reset phy + -- MDIO + mdio_i => et_phy1_mdio_in, + mdio_o => et_phy1_mdio_out, + mdio_oe_o => et_phy1_mdio_oe, + mdc_o => et_phy1_mdc_o + ); + + --! MDIO bidirectional data buffer + mdio_data_buf : bibuf_async + port map( + oe => et_phy1_mdio_oe, + io => et_phy1_mdio_io, + inp => et_phy1_mdio_out, + outp => et_phy1_mdio_in + ); + --@} end rtl; diff --git a/quartus/dionysos_nios2mmu.bsf b/quartus/dionysos_nios2mmu.bsf index fb0209d..64435b0 100644 --- a/quartus/dionysos_nios2mmu.bsf +++ b/quartus/dionysos_nios2mmu.bsf @@ -1,8 +1,8 @@ (header "symbol" (version "1.1")) (symbol -(rect 0 0 448 432) +(rect 0 0 528 656) (text "dionysos_nios2mmu" (rect 4 0 136 16)(font "Arial" (font_size 10))) -(text "inst" (rect 4 416 28 432)(font "Arial")) +(text "inst" (rect 4 640 28 656)(font "Arial")) (port (pt 0 32) (input) @@ -27,140 +27,309 @@ (port (pt 0 400) (input) +(text "gm_rx_d_to_the_triple_speed_ethernet_0[7..0] " (rect 0 0 225 16)(font "Arial" (font_size 8))) +(text "gm_rx_d_to_the_triple_speed_ethernet_0[7..0] " (rect 20 393 245 409)(font "Arial" (font_size 8))) +(line (pt 0 400)(pt 16 400)(line_width 3)) +) +(port +(pt 0 416) +(input) +(text "gm_rx_dv_to_the_triple_speed_ethernet_0 " (rect 0 0 206 16)(font "Arial" (font_size 8))) +(text "gm_rx_dv_to_the_triple_speed_ethernet_0 " (rect 20 409 226 425)(font "Arial" (font_size 8))) +(line (pt 0 416)(pt 16 416)(line_width 1)) +) +(port +(pt 0 432) +(input) +(text "gm_rx_err_to_the_triple_speed_ethernet_0 " (rect 0 0 208 16)(font "Arial" (font_size 8))) +(text "gm_rx_err_to_the_triple_speed_ethernet_0 " (rect 20 425 228 441)(font "Arial" (font_size 8))) +(line (pt 0 432)(pt 16 432)(line_width 1)) +) +(port +(pt 0 448) +(input) +(text "m_rx_col_to_the_triple_speed_ethernet_0 " (rect 0 0 203 16)(font "Arial" (font_size 8))) +(text "m_rx_col_to_the_triple_speed_ethernet_0 " (rect 20 441 223 457)(font "Arial" (font_size 8))) +(line (pt 0 448)(pt 16 448)(line_width 1)) +) +(port +(pt 0 464) +(input) +(text "m_rx_crs_to_the_triple_speed_ethernet_0 " (rect 0 0 203 16)(font "Arial" (font_size 8))) +(text "m_rx_crs_to_the_triple_speed_ethernet_0 " (rect 20 457 223 473)(font "Arial" (font_size 8))) +(line (pt 0 464)(pt 16 464)(line_width 1)) +) +(port +(pt 0 480) +(input) +(text "m_rx_d_to_the_triple_speed_ethernet_0[3..0] " (rect 0 0 219 16)(font "Arial" (font_size 8))) +(text "m_rx_d_to_the_triple_speed_ethernet_0[3..0] " (rect 20 473 239 489)(font "Arial" (font_size 8))) +(line (pt 0 480)(pt 16 480)(line_width 3)) +) +(port +(pt 0 496) +(input) +(text "m_rx_en_to_the_triple_speed_ethernet_0 " (rect 0 0 201 16)(font "Arial" (font_size 8))) +(text "m_rx_en_to_the_triple_speed_ethernet_0 " (rect 20 489 221 505)(font "Arial" (font_size 8))) +(line (pt 0 496)(pt 16 496)(line_width 1)) +) +(port +(pt 0 512) +(input) +(text "m_rx_err_to_the_triple_speed_ethernet_0 " (rect 0 0 202 16)(font "Arial" (font_size 8))) +(text "m_rx_err_to_the_triple_speed_ethernet_0 " (rect 20 505 222 521)(font "Arial" (font_size 8))) +(line (pt 0 512)(pt 16 512)(line_width 1)) +) +(port +(pt 0 528) +(input) +(text "mdio_in_to_the_triple_speed_ethernet_0 " (rect 0 0 198 16)(font "Arial" (font_size 8))) +(text "mdio_in_to_the_triple_speed_ethernet_0 " (rect 20 521 218 537)(font "Arial" (font_size 8))) +(line (pt 0 528)(pt 16 528)(line_width 1)) +) +(port +(pt 0 544) +(input) +(text "rx_clk_to_the_triple_speed_ethernet_0 " (rect 0 0 187 16)(font "Arial" (font_size 8))) +(text "rx_clk_to_the_triple_speed_ethernet_0 " (rect 20 537 207 553)(font "Arial" (font_size 8))) +(line (pt 0 544)(pt 16 544)(line_width 1)) +) +(port +(pt 0 560) +(input) +(text "set_1000_to_the_triple_speed_ethernet_0 " (rect 0 0 205 16)(font "Arial" (font_size 8))) +(text "set_1000_to_the_triple_speed_ethernet_0 " (rect 20 553 225 569)(font "Arial" (font_size 8))) +(line (pt 0 560)(pt 16 560)(line_width 1)) +) +(port +(pt 0 576) +(input) +(text "set_10_to_the_triple_speed_ethernet_0 " (rect 0 0 192 16)(font "Arial" (font_size 8))) +(text "set_10_to_the_triple_speed_ethernet_0 " (rect 20 569 212 585)(font "Arial" (font_size 8))) +(line (pt 0 576)(pt 16 576)(line_width 1)) +) +(port +(pt 0 592) +(input) +(text "tx_clk_to_the_triple_speed_ethernet_0 " (rect 0 0 186 16)(font "Arial" (font_size 8))) +(text "tx_clk_to_the_triple_speed_ethernet_0 " (rect 20 585 206 601)(font "Arial" (font_size 8))) +(line (pt 0 592)(pt 16 592)(line_width 1)) +) +(port +(pt 0 624) +(input) (text "rxd_to_the_uart_0 " (rect 0 0 87 16)(font "Arial" (font_size 8))) -(text "rxd_to_the_uart_0 " (rect 20 393 107 409)(font "Arial" (font_size 8))) -(line (pt 0 400)(pt 16 400)(line_width 1)) +(text "rxd_to_the_uart_0 " (rect 20 617 107 633)(font "Arial" (font_size 8))) +(line (pt 0 624)(pt 16 624)(line_width 1)) ) (port -(pt 448 80) +(pt 528 80) (output) (text "dclk_from_the_epcs_flash_controller_0 " (rect 0 0 188 16)(font "Arial" (font_size 8))) -(text "dclk_from_the_epcs_flash_controller_0 " (rect 233 73 421 89)(font "Arial" (font_size 8))) -(line (pt 432 80)(pt 448 80)(line_width 1)) +(text "dclk_from_the_epcs_flash_controller_0 " (rect 313 73 501 89)(font "Arial" (font_size 8))) +(line (pt 512 80)(pt 528 80)(line_width 1)) ) (port -(pt 448 96) +(pt 528 96) (output) (text "sce_from_the_epcs_flash_controller_0 " (rect 0 0 186 16)(font "Arial" (font_size 8))) -(text "sce_from_the_epcs_flash_controller_0 " (rect 235 89 421 105)(font "Arial" (font_size 8))) -(line (pt 432 96)(pt 448 96)(line_width 1)) +(text "sce_from_the_epcs_flash_controller_0 " (rect 315 89 501 105)(font "Arial" (font_size 8))) +(line (pt 512 96)(pt 528 96)(line_width 1)) ) (port -(pt 448 112) +(pt 528 112) (output) (text "sdo_from_the_epcs_flash_controller_0 " (rect 0 0 186 16)(font "Arial" (font_size 8))) -(text "sdo_from_the_epcs_flash_controller_0 " (rect 234 105 421 121)(font "Arial" (font_size 8))) -(line (pt 432 112)(pt 448 112)(line_width 1)) +(text "sdo_from_the_epcs_flash_controller_0 " (rect 314 105 501 121)(font "Arial" (font_size 8))) +(line (pt 512 112)(pt 528 112)(line_width 1)) ) (port -(pt 448 144) +(pt 528 144) (output) (text "zs_addr_from_the_sdram_0[11..0] " (rect 0 0 165 16)(font "Arial" (font_size 8))) -(text "zs_addr_from_the_sdram_0[11..0] " (rect 255 137 421 153)(font "Arial" (font_size 8))) -(line (pt 432 144)(pt 448 144)(line_width 3)) +(text "zs_addr_from_the_sdram_0[11..0] " (rect 335 137 501 153)(font "Arial" (font_size 8))) +(line (pt 512 144)(pt 528 144)(line_width 3)) ) (port -(pt 448 160) +(pt 528 160) (output) (text "zs_ba_from_the_sdram_0[1..0] " (rect 0 0 150 16)(font "Arial" (font_size 8))) -(text "zs_ba_from_the_sdram_0[1..0] " (rect 271 153 421 169)(font "Arial" (font_size 8))) -(line (pt 432 160)(pt 448 160)(line_width 3)) +(text "zs_ba_from_the_sdram_0[1..0] " (rect 351 153 501 169)(font "Arial" (font_size 8))) +(line (pt 512 160)(pt 528 160)(line_width 3)) ) (port -(pt 448 176) +(pt 528 176) (output) (text "zs_cas_n_from_the_sdram_0 " (rect 0 0 143 16)(font "Arial" (font_size 8))) -(text "zs_cas_n_from_the_sdram_0 " (rect 278 169 421 185)(font "Arial" (font_size 8))) -(line (pt 432 176)(pt 448 176)(line_width 1)) +(text "zs_cas_n_from_the_sdram_0 " (rect 358 169 501 185)(font "Arial" (font_size 8))) +(line (pt 512 176)(pt 528 176)(line_width 1)) ) (port -(pt 448 192) +(pt 528 192) (output) (text "zs_cke_from_the_sdram_0 " (rect 0 0 131 16)(font "Arial" (font_size 8))) -(text "zs_cke_from_the_sdram_0 " (rect 290 185 421 201)(font "Arial" (font_size 8))) -(line (pt 432 192)(pt 448 192)(line_width 1)) +(text "zs_cke_from_the_sdram_0 " (rect 370 185 501 201)(font "Arial" (font_size 8))) +(line (pt 512 192)(pt 528 192)(line_width 1)) ) (port -(pt 448 208) +(pt 528 208) (output) (text "zs_cs_n_from_the_sdram_0 " (rect 0 0 137 16)(font "Arial" (font_size 8))) -(text "zs_cs_n_from_the_sdram_0 " (rect 284 201 421 217)(font "Arial" (font_size 8))) -(line (pt 432 208)(pt 448 208)(line_width 1)) +(text "zs_cs_n_from_the_sdram_0 " (rect 364 201 501 217)(font "Arial" (font_size 8))) +(line (pt 512 208)(pt 528 208)(line_width 1)) ) (port -(pt 448 224) +(pt 528 224) (bidir) (text "zs_dq_to_and_from_the_sdram_0[15..0] " (rect 0 0 195 16)(font "Arial" (font_size 8))) -(text "zs_dq_to_and_from_the_sdram_0[15..0] " (rect 226 217 421 233)(font "Arial" (font_size 8))) -(line (pt 432 224)(pt 448 224)(line_width 3)) +(text "zs_dq_to_and_from_the_sdram_0[15..0] " (rect 306 217 501 233)(font "Arial" (font_size 8))) +(line (pt 512 224)(pt 528 224)(line_width 3)) ) (port -(pt 448 240) +(pt 528 240) (output) (text "zs_dqm_from_the_sdram_0[1..0] " (rect 0 0 159 16)(font "Arial" (font_size 8))) -(text "zs_dqm_from_the_sdram_0[1..0] " (rect 262 233 421 249)(font "Arial" (font_size 8))) -(line (pt 432 240)(pt 448 240)(line_width 3)) +(text "zs_dqm_from_the_sdram_0[1..0] " (rect 342 233 501 249)(font "Arial" (font_size 8))) +(line (pt 512 240)(pt 528 240)(line_width 3)) ) (port -(pt 448 256) +(pt 528 256) (output) (text "zs_ras_n_from_the_sdram_0 " (rect 0 0 141 16)(font "Arial" (font_size 8))) -(text "zs_ras_n_from_the_sdram_0 " (rect 280 249 421 265)(font "Arial" (font_size 8))) -(line (pt 432 256)(pt 448 256)(line_width 1)) +(text "zs_ras_n_from_the_sdram_0 " (rect 360 249 501 265)(font "Arial" (font_size 8))) +(line (pt 512 256)(pt 528 256)(line_width 1)) ) (port -(pt 448 272) +(pt 528 272) (output) (text "zs_we_n_from_the_sdram_0 " (rect 0 0 139 16)(font "Arial" (font_size 8))) -(text "zs_we_n_from_the_sdram_0 " (rect 282 265 421 281)(font "Arial" (font_size 8))) -(line (pt 432 272)(pt 448 272)(line_width 1)) +(text "zs_we_n_from_the_sdram_0 " (rect 362 265 501 281)(font "Arial" (font_size 8))) +(line (pt 512 272)(pt 528 272)(line_width 1)) ) (port -(pt 448 304) +(pt 528 304) (output) (text "select_n_to_the_cfi_flash_0 " (rect 0 0 134 16)(font "Arial" (font_size 8))) -(text "select_n_to_the_cfi_flash_0 " (rect 287 297 421 313)(font "Arial" (font_size 8))) -(line (pt 432 304)(pt 448 304)(line_width 1)) +(text "select_n_to_the_cfi_flash_0 " (rect 367 297 501 313)(font "Arial" (font_size 8))) +(line (pt 512 304)(pt 528 304)(line_width 1)) ) (port -(pt 448 320) +(pt 528 320) (output) (text "tri_state_bridge_0_address[21..0] " (rect 0 0 163 16)(font "Arial" (font_size 8))) -(text "tri_state_bridge_0_address[21..0] " (rect 257 313 421 329)(font "Arial" (font_size 8))) -(line (pt 432 320)(pt 448 320)(line_width 3)) +(text "tri_state_bridge_0_address[21..0] " (rect 337 313 501 329)(font "Arial" (font_size 8))) +(line (pt 512 320)(pt 528 320)(line_width 3)) ) (port -(pt 448 336) +(pt 528 336) (bidir) (text "tri_state_bridge_0_data[7..0] " (rect 0 0 139 16)(font "Arial" (font_size 8))) -(text "tri_state_bridge_0_data[7..0] " (rect 282 329 421 345)(font "Arial" (font_size 8))) -(line (pt 432 336)(pt 448 336)(line_width 3)) +(text "tri_state_bridge_0_data[7..0] " (rect 362 329 501 345)(font "Arial" (font_size 8))) +(line (pt 512 336)(pt 528 336)(line_width 3)) ) (port -(pt 448 352) +(pt 528 352) (output) (text "tri_state_bridge_0_readn " (rect 0 0 122 16)(font "Arial" (font_size 8))) -(text "tri_state_bridge_0_readn " (rect 299 345 421 361)(font "Arial" (font_size 8))) -(line (pt 432 352)(pt 448 352)(line_width 1)) +(text "tri_state_bridge_0_readn " (rect 379 345 501 361)(font "Arial" (font_size 8))) +(line (pt 512 352)(pt 528 352)(line_width 1)) ) (port -(pt 448 368) +(pt 528 368) (output) (text "write_n_to_the_cfi_flash_0 " (rect 0 0 128 16)(font "Arial" (font_size 8))) -(text "write_n_to_the_cfi_flash_0 " (rect 292 361 421 377)(font "Arial" (font_size 8))) -(line (pt 432 368)(pt 448 368)(line_width 1)) +(text "write_n_to_the_cfi_flash_0 " (rect 372 361 501 377)(font "Arial" (font_size 8))) +(line (pt 512 368)(pt 528 368)(line_width 1)) +) +(port +(pt 528 400) +(output) +(text "ena_10_from_the_triple_speed_ethernet_0 " (rect 0 0 208 16)(font "Arial" (font_size 8))) +(text "ena_10_from_the_triple_speed_ethernet_0 " (rect 292 393 501 409)(font "Arial" (font_size 8))) +(line (pt 512 400)(pt 528 400)(line_width 1)) +) +(port +(pt 528 416) +(output) +(text "eth_mode_from_the_triple_speed_ethernet_0 " (rect 0 0 220 16)(font "Arial" (font_size 8))) +(text "eth_mode_from_the_triple_speed_ethernet_0 " (rect 281 409 501 425)(font "Arial" (font_size 8))) +(line (pt 512 416)(pt 528 416)(line_width 1)) +) +(port +(pt 528 432) +(output) +(text "gm_tx_d_from_the_triple_speed_ethernet_0[7..0] " (rect 0 0 237 16)(font "Arial" (font_size 8))) +(text "gm_tx_d_from_the_triple_speed_ethernet_0[7..0] " (rect 264 425 501 441)(font "Arial" (font_size 8))) +(line (pt 512 432)(pt 528 432)(line_width 3)) +) +(port +(pt 528 448) +(output) +(text "gm_tx_en_from_the_triple_speed_ethernet_0 " (rect 0 0 219 16)(font "Arial" (font_size 8))) +(text "gm_tx_en_from_the_triple_speed_ethernet_0 " (rect 282 441 501 457)(font "Arial" (font_size 8))) +(line (pt 512 448)(pt 528 448)(line_width 1)) +) +(port +(pt 528 464) +(output) +(text "gm_tx_err_from_the_triple_speed_ethernet_0 " (rect 0 0 220 16)(font "Arial" (font_size 8))) +(text "gm_tx_err_from_the_triple_speed_ethernet_0 " (rect 281 457 501 473)(font "Arial" (font_size 8))) +(line (pt 512 464)(pt 528 464)(line_width 1)) +) +(port +(pt 528 480) +(output) +(text "m_tx_d_from_the_triple_speed_ethernet_0[3..0] " (rect 0 0 230 16)(font "Arial" (font_size 8))) +(text "m_tx_d_from_the_triple_speed_ethernet_0[3..0] " (rect 270 473 501 489)(font "Arial" (font_size 8))) +(line (pt 512 480)(pt 528 480)(line_width 3)) +) +(port +(pt 528 496) +(output) +(text "m_tx_en_from_the_triple_speed_ethernet_0 " (rect 0 0 212 16)(font "Arial" (font_size 8))) +(text "m_tx_en_from_the_triple_speed_ethernet_0 " (rect 288 489 501 505)(font "Arial" (font_size 8))) +(line (pt 512 496)(pt 528 496)(line_width 1)) +) +(port +(pt 528 512) +(output) +(text "m_tx_err_from_the_triple_speed_ethernet_0 " (rect 0 0 214 16)(font "Arial" (font_size 8))) +(text "m_tx_err_from_the_triple_speed_ethernet_0 " (rect 287 505 501 521)(font "Arial" (font_size 8))) +(line (pt 512 512)(pt 528 512)(line_width 1)) +) +(port +(pt 528 528) +(output) +(text "mdc_from_the_triple_speed_ethernet_0 " (rect 0 0 192 16)(font "Arial" (font_size 8))) +(text "mdc_from_the_triple_speed_ethernet_0 " (rect 308 521 501 537)(font "Arial" (font_size 8))) +(line (pt 512 528)(pt 528 528)(line_width 1)) +) +(port +(pt 528 544) +(output) +(text "mdio_oen_from_the_triple_speed_ethernet_0 " (rect 0 0 220 16)(font "Arial" (font_size 8))) +(text "mdio_oen_from_the_triple_speed_ethernet_0 " (rect 281 537 501 553)(font "Arial" (font_size 8))) +(line (pt 512 544)(pt 528 544)(line_width 1)) +) +(port +(pt 528 560) +(output) +(text "mdio_out_from_the_triple_speed_ethernet_0 " (rect 0 0 217 16)(font "Arial" (font_size 8))) +(text "mdio_out_from_the_triple_speed_ethernet_0 " (rect 284 553 501 569)(font "Arial" (font_size 8))) +(line (pt 512 560)(pt 528 560)(line_width 1)) ) (port -(pt 448 400) +(pt 528 624) (output) (text "txd_from_the_uart_0 " (rect 0 0 98 16)(font "Arial" (font_size 8))) -(text "txd_from_the_uart_0 " (rect 322 393 421 409)(font "Arial" (font_size 8))) -(line (pt 432 400)(pt 448 400)(line_width 1)) +(text "txd_from_the_uart_0 " (rect 402 617 501 633)(font "Arial" (font_size 8))) +(line (pt 512 624)(pt 528 624)(line_width 1)) ) (drawing -(line (pt 16 64)(pt 431 64)(color 0 0 0)(dotted)(line_width 1)) -(line (pt 16 128)(pt 431 128)(color 0 0 0)(dotted)(line_width 1)) -(line (pt 16 288)(pt 431 288)(color 0 0 0)(dotted)(line_width 1)) -(line (pt 16 384)(pt 431 384)(color 0 0 0)(dotted)(line_width 1)) -(rectangle (rect 16 16 432 416)(line_width 1))) +(line (pt 16 64)(pt 511 64)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 128)(pt 511 128)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 288)(pt 511 288)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 384)(pt 511 384)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 608)(pt 511 608)(color 0 0 0)(dotted)(line_width 1)) +(rectangle (rect 16 16 512 640)(line_width 1))) ) diff --git a/quartus/dionysos_nios2mmu.qsf b/quartus/dionysos_nios2mmu.qsf index 2aa3d7f..de2936f 100644 --- a/quartus/dionysos_nios2mmu.qsf +++ b/quartus/dionysos_nios2mmu.qsf @@ -54,18 +54,18 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL # Clock inputs # ------------ set_location_assignment PIN_G2 -to clock_50_i -#set_location_assignment PIN_T2 -to et_phy1_tx_clk_1_i -#set_location_assignment PIN_T1 -to et_phy1_rx_clk_1_i +set_location_assignment PIN_T2 -to et_phy1_tx_clk_1_i +set_location_assignment PIN_T1 -to et_phy1_rx_clk_1_i #set_location_assignment PIN_G21 -to usb_clk_i #set_location_assignment PIN_G22 -to sdfe_clk_20mhz_i -#set_location_assignment PIN_T21 -to et_phy2_rx_clk_2_i -#set_location_assignment PIN_T22 -to et_phy2_tx_clk_2_i +set_location_assignment PIN_T21 -to et_phy2_rx_clk_2_i +set_location_assignment PIN_T22 -to et_phy2_tx_clk_2_i set_location_assignment PIN_A12 -to aux_clk_n_i set_location_assignment PIN_B12 -to aux_clk_p_i -#set_location_assignment PIN_AB12 -to et_phy2_rx_clk_1_i -#set_location_assignment PIN_AA12 -to et_phy2_tx_clk_1_i -#set_location_assignment PIN_AB11 -to et_phy1_rx_clk_2_i -#set_location_assignment PIN_AA11 -to et_phy1_tx_clk_2_i +set_location_assignment PIN_AB12 -to et_phy2_rx_clk_1_i +set_location_assignment PIN_AA12 -to et_phy2_tx_clk_1_i +set_location_assignment PIN_AB11 -to et_phy1_rx_clk_2_i +set_location_assignment PIN_AA11 -to et_phy1_tx_clk_2_i # FPGA programming pins # --------------------- @@ -152,32 +152,32 @@ set_location_assignment PIN_J2 -to gp_led_o[3] # FPGA bank 3 # ----------- -#set_location_assignment PIN_V5 -to et_phy1_rx_dv_1_i -#set_location_assignment PIN_U7 -to et_phy1_rx_er_1_i -#set_location_assignment PIN_U8 -to et_phy1_crs_1_i -#set_location_assignment PIN_Y4 -to et_phy1_rxd_1_i[0] -#set_location_assignment PIN_Y3 -to et_phy1_rxd_1_i[1] -#set_location_assignment PIN_Y6 -to et_phy1_rxd_1_i[2] +set_location_assignment PIN_V5 -to et_phy1_rx_dv_1_i +set_location_assignment PIN_U7 -to et_phy1_rx_er_1_i +set_location_assignment PIN_U8 -to et_phy1_crs_1_i +set_location_assignment PIN_Y4 -to et_phy1_rxd_1_i[0] +set_location_assignment PIN_Y3 -to et_phy1_rxd_1_i[1] +set_location_assignment PIN_Y6 -to et_phy1_rxd_1_i[2] #set_location_assignment PIN_AA3 -to ssram_clk_o -set_location_assignment PIN_AB3 -to reserve7_i -#set_location_assignment PIN_W6 -to et_phy1_rxd_1_i[3] -#set_location_assignment PIN_V7 -to et_phy1_col_1_i -#set_location_assignment PIN_AB4 -to et_phy1_tx_en_1_o -#set_location_assignment PIN_AA5 -to et_phy1_txd_1_o[0] -#set_location_assignment PIN_AB5 -to et_phy1_txd_1_o[1] -#set_location_assignment PIN_T8 -to et_phy1_txd_1_o[2] -#set_location_assignment PIN_T9 -to et_phy1_txd_1_o[3] -#set_location_assignment PIN_W7 -to et_phy1_int_1_i -set_location_assignment PIN_Y7 -to reserve2_i -#set_location_assignment PIN_U9 -to et_phy1_rx_dv_2_i -#set_location_assignment PIN_V8 -to et_phy1_rx_er_2_i -#set_location_assignment PIN_W8 -to et_phy1_crs_2_i -#set_location_assignment PIN_AA7 -to et_phy1_rxd_2_i[0] -#set_location_assignment PIN_AB7 -to et_phy1_rxd_2_i[1] -#set_location_assignment PIN_Y8 -to et_phy1_rxd_2_i[2] -#set_location_assignment PIN_T10 -to et_phy1_rxd_2_i[3] -#set_location_assignment PIN_T11 -to et_phy1_col_2_i -set_location_assignment PIN_V9 -to reserve3_i +#set_location_assignment PIN_AB3 -to reserve7_i +set_location_assignment PIN_W6 -to et_phy1_rxd_1_i[3] +set_location_assignment PIN_V7 -to et_phy1_col_1_i +set_location_assignment PIN_AB4 -to et_phy1_tx_en_1_o +set_location_assignment PIN_AA5 -to et_phy1_txd_1_o[0] +set_location_assignment PIN_AB5 -to et_phy1_txd_1_o[1] +set_location_assignment PIN_T8 -to et_phy1_txd_1_o[2] +set_location_assignment PIN_T9 -to et_phy1_txd_1_o[3] +set_location_assignment PIN_W7 -to et_phy1_int_1_i +#set_location_assignment PIN_Y7 -to reserve2_i +set_location_assignment PIN_U9 -to et_phy1_rx_dv_2_i +set_location_assignment PIN_V8 -to et_phy1_rx_er_2_i +set_location_assignment PIN_W8 -to et_phy1_crs_2_i +set_location_assignment PIN_AA7 -to et_phy1_rxd_2_i[0] +set_location_assignment PIN_AB7 -to et_phy1_rxd_2_i[1] +set_location_assignment PIN_Y8 -to et_phy1_rxd_2_i[2] +set_location_assignment PIN_T10 -to et_phy1_rxd_2_i[3] +set_location_assignment PIN_T11 -to et_phy1_col_2_i +#set_location_assignment PIN_V9 -to reserve3_i set_location_assignment PIN_V10 -to et_phy1_tx_en_2_o set_location_assignment PIN_U10 -to et_phy1_txd_2_o[0] set_location_assignment PIN_AA8 -to et_phy1_txd_2_o[1] @@ -186,9 +186,9 @@ set_location_assignment PIN_AA9 -to et_phy1_txd_2_o[3] set_location_assignment PIN_AB9 -to et_phy1_int_2_i set_location_assignment PIN_U11 -to et_phy1_mdc_o set_location_assignment PIN_V11 -to et_phy1_mdio_io -#set_location_assignment PIN_W10 -to rst_et_phy1_n_o -set_location_assignment PIN_Y10 -to gen_led_r_o[3] -set_location_assignment PIN_AA10 -to gen_led_g_o[3] +set_location_assignment PIN_W10 -to rst_et_phy1_n_o +#set_location_assignment PIN_Y10 -to gen_led_r_o[3] +#set_location_assignment PIN_AA10 -to gen_led_g_o[3] # FPGA bank 4 # ----------- @@ -220,42 +220,42 @@ set_location_assignment PIN_AA10 -to gen_led_g_o[3] #set_location_assignment PIN_AA17 -to otg_dreq1_i #set_location_assignment PIN_AB17 -to otg_dack0_n_o #set_location_assignment PIN_AA18 -to otg_dack1_n_o -#set_location_assignment PIN_AB19 -to et_phy2_rx_dv_1_i -set_location_assignment PIN_W17 -to gen_led_r_o[6] -#set_location_assignment PIN_Y17 -to et_phy2_tx_en_1_o -set_location_assignment PIN_AB20 -to gen_led_r_o[2] -set_location_assignment PIN_V16 -to gen_led_g_o[2] -set_location_assignment PIN_U16 -to reserve4_i -set_location_assignment PIN_U17 -to reserve5_i +set_location_assignment PIN_AB19 -to et_phy2_rx_dv_1_i +#set_location_assignment PIN_W17 -to gen_led_r_o[6] +set_location_assignment PIN_Y17 -to et_phy2_tx_en_1_o +#set_location_assignment PIN_AB20 -to gen_led_r_o[2] +#set_location_assignment PIN_V16 -to gen_led_g_o[2] +#set_location_assignment PIN_U16 -to reserve4_i +#set_location_assignment PIN_U17 -to reserve5_i set_location_assignment PIN_T16 -to aux_clk_p_o set_location_assignment PIN_R16 -to aux_clk_n_o -set_location_assignment PIN_R15 -to gen_led_g_o[6] +#set_location_assignment PIN_R15 -to gen_led_g_o[6] # FPGA bank 5 # ----------- -#set_location_assignment PIN_AA22 -to et_phy2_txd_2_o[3] -#set_location_assignment PIN_AA21 -to et_phy2_txd_2_o[2] -#set_location_assignment PIN_T17 -to et_phy2_txd_2_o[1] -#set_location_assignment PIN_T18 -to et_phy2_txd_2_o[0] -#set_location_assignment PIN_W20 -to et_phy2_txd_1_o[3] -#set_location_assignment PIN_W19 -to et_phy2_txd_1_o[2] -#set_location_assignment PIN_Y22 -to et_phy2_txd_1_o[1] -#set_location_assignment PIN_Y21 -to et_phy2_txd_1_o[0] -#set_location_assignment PIN_U20 -to et_phy2_rxd_2_i[3] -#set_location_assignment PIN_U19 -to et_phy2_rxd_2_i[2] -#set_location_assignment PIN_W22 -to et_phy2_rxd_2_i[1] -#set_location_assignment PIN_W21 -to et_phy2_rxd_2_i[0] -#set_location_assignment PIN_P15 -to et_phy2_rxd_1_i[3] -#set_location_assignment PIN_P16 -to et_phy2_rxd_1_i[2] -#set_location_assignment PIN_R17 -to et_phy2_rxd_1_i[1] -#set_location_assignment PIN_P17 -to et_phy2_rxd_1_i[0] -#set_location_assignment PIN_V22 -to et_phy2_rx_er_1_i -#set_location_assignment PIN_V21 -to et_phy2_crs_2_i -#set_location_assignment PIN_R20 -to rst_et_phy2_n_o -#set_location_assignment PIN_U22 -to et_phy2_rx_er_2_i -#set_location_assignment PIN_U21 -to et_phy2_col_2_i -#set_location_assignment PIN_R18 -to et_phy2_crs_1_i -#set_location_assignment PIN_R19 -to et_phy2_col_1_i +set_location_assignment PIN_AA22 -to et_phy2_txd_2_o[3] +set_location_assignment PIN_AA21 -to et_phy2_txd_2_o[2] +set_location_assignment PIN_T17 -to et_phy2_txd_2_o[1] +set_location_assignment PIN_T18 -to et_phy2_txd_2_o[0] +set_location_assignment PIN_W20 -to et_phy2_txd_1_o[3] +set_location_assignment PIN_W19 -to et_phy2_txd_1_o[2] +set_location_assignment PIN_Y22 -to et_phy2_txd_1_o[1] +set_location_assignment PIN_Y21 -to et_phy2_txd_1_o[0] +set_location_assignment PIN_U20 -to et_phy2_rxd_2_i[3] +set_location_assignment PIN_U19 -to et_phy2_rxd_2_i[2] +set_location_assignment PIN_W22 -to et_phy2_rxd_2_i[1] +set_location_assignment PIN_W21 -to et_phy2_rxd_2_i[0] +set_location_assignment PIN_P15 -to et_phy2_rxd_1_i[3] +set_location_assignment PIN_P16 -to et_phy2_rxd_1_i[2] +set_location_assignment PIN_R17 -to et_phy2_rxd_1_i[1] +set_location_assignment PIN_P17 -to et_phy2_rxd_1_i[0] +set_location_assignment PIN_V22 -to et_phy2_rx_er_1_i +set_location_assignment PIN_V21 -to et_phy2_crs_2_i +set_location_assignment PIN_R20 -to rst_et_phy2_n_o +set_location_assignment PIN_U22 -to et_phy2_rx_er_2_i +set_location_assignment PIN_U21 -to et_phy2_col_2_i +set_location_assignment PIN_R18 -to et_phy2_crs_1_i +set_location_assignment PIN_R19 -to et_phy2_col_1_i #set_location_assignment PIN_N16 -to mpd_io[0] #set_location_assignment PIN_R22 -to mpd_io[1] #set_location_assignment PIN_R21 -to mpd_io[2] @@ -266,12 +266,12 @@ set_location_assignment PIN_R15 -to gen_led_g_o[6] #set_location_assignment PIN_N19 -to mpd_io[7] set_location_assignment PIN_N18 -to reserve6_i set_location_assignment PIN_N21 -to fpga_reset_n_i -#set_location_assignment PIN_M22 -to et_phy2_rx_dv_2_i -#set_location_assignment PIN_M21 -to et_phy2_tx_en_2_o -#set_location_assignment PIN_AA20 -to et_phy2_int_1_i -#set_location_assignment PIN_M20 -to et_phy2_int_2_i -#set_location_assignment PIN_M19 -to et_phy2_mdc_o -#set_location_assignment PIN_M16 -to et_phy2_mdio_io +set_location_assignment PIN_M22 -to et_phy2_rx_dv_2_i +set_location_assignment PIN_M21 -to et_phy2_tx_en_2_o +set_location_assignment PIN_AA20 -to et_phy2_int_1_i +set_location_assignment PIN_M20 -to et_phy2_int_2_i +set_location_assignment PIN_M19 -to et_phy2_mdc_o +set_location_assignment PIN_M16 -to et_phy2_mdio_io # FPGA bank 6 # ----------- @@ -364,7 +364,7 @@ set_location_assignment PIN_F11 -to dram_a_o[12] #set_location_assignment PIN_C10 -to sdfe_aux_0_4_i #set_location_assignment PIN_G11 -to sdfe_aux_0_5_i #set_location_assignment PIN_A8 -to sdfe_refclk_0_i -set_location_assignment PIN_B8 -to reserve8_i +#set_location_assignment PIN_B8 -to reserve8_i #set_location_assignment PIN_B7 -to sdfe_dout_3_i #set_location_assignment PIN_A6 -to sdfe_din_3_o #set_location_assignment PIN_B6 -to sdfe_aux_3_0_o @@ -374,8 +374,8 @@ set_location_assignment PIN_B8 -to reserve8_i #set_location_assignment PIN_H11 -to sdfe_aux_3_4_i #set_location_assignment PIN_H10 -to sdfe_aux_3_5_i #set_location_assignment PIN_A5 -to sdfe_refclk_3_i -set_location_assignment PIN_B5 -to gen_led_r_o[1] -set_location_assignment PIN_G10 -to gen_led_g_o[1] +#set_location_assignment PIN_B5 -to gen_led_r_o[1] +#set_location_assignment PIN_G10 -to gen_led_g_o[1] #set_location_assignment PIN_F10 -to sdfe_scdi_o #set_location_assignment PIN_C6 -to sdfe_scdo_i #set_location_assignment PIN_D7 -to sdfe_scck_o @@ -392,7 +392,7 @@ set_location_assignment PIN_G10 -to gen_led_g_o[1] #set_location_assignment PIN_F7 -to mpad_o[2] #set_location_assignment PIN_G7 -to mpad_o[3] #set_location_assignment PIN_F9 -to mpad_o[4] -#set_location_assignment PIN_E5 -to et_phy_clk_50mhz_o +set_location_assignment PIN_E5 -to et_phy_clk_50mhz_o # EDA Netlist Writer Assignments # ============================== @@ -429,6 +429,17 @@ set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + + + + +set_global_assignment -name VHDL_FILE ../lib/ethernet/components/rmii_phy_to_mii_mac.vhd +set_global_assignment -name VHDL_FILE ../lib/misc/components/bibuf_async.vhd +set_global_assignment -name VHDL_FILE ../lib/misc/ines_vhdl_lib_base_pkg.vhd +set_global_assignment -name VHDL_FILE ../lib/misc/reduce_pkg.vhd +set_global_assignment -name VHDL_FILE ../lib/ethernet/components/mii_management_transmit.vhd +set_global_assignment -name VHDL_FILE ../lib/ethernet/components/mdio_interface.vhd +set_global_assignment -name VHDL_FILE ../lib/ethernet/components/rmii_in_out.vhd set_global_assignment -name QIP_FILE ../lib/altera/sinet_pll.qip set_global_assignment -name VHDL_FILE ../lib/misc/components/reset_sync.vhd set_global_assignment -name VHDL_FILE ../dionysos_top.vhd @@ -436,5 +447,4 @@ set_global_assignment -name QIP_FILE dionysos_nios2mmu.qip set_global_assignment -name VHDL_FILE dionysos_nios2mmu.vhd set_global_assignment -name SDC_FILE dionysos_nios2mmu.sdc - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/quartus/dionysos_nios2mmu.sopc b/quartus/dionysos_nios2mmu.sopc index 02ecb7e..802aed8 100644 --- a/quartus/dionysos_nios2mmu.sopc +++ b/quartus/dionysos_nios2mmu.sopc @@ -31,6 +31,14 @@ type = "int"; } } + element triple_speed_ethernet_0.control_port + { + datum baseAddress + { + value = "0"; + type = "long"; + } + } element cpu_0 { datum _sortIndex @@ -44,6 +52,35 @@ type = "String"; } } + element sgdma_rx.csr + { + datum baseAddress + { + value = "1024"; + type = "long"; + } + } + element sgdma_tx.csr + { + datum baseAddress + { + value = "1088"; + type = "long"; + } + } + element descriptor_memory + { + datum _sortIndex + { + value = "13"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } element dionysos_nios2mmu { } @@ -102,19 +139,16 @@ type = "String"; } } - element onchip_memory2_0.s1 + element sdram_0.s1 { - datum baseAddress + datum _lockedAddress { - value = "41951232"; - type = "long"; + value = "0"; + type = "boolean"; } - } - element uart_0.s1 - { datum baseAddress { - value = "41952288"; + value = "16777216"; type = "long"; } } @@ -126,16 +160,19 @@ type = "long"; } } - element sdram_0.s1 + element uart_0.s1 { - datum _lockedAddress + datum baseAddress { - value = "0"; - type = "boolean"; + value = "41952288"; + type = "long"; } + } + element descriptor_memory.s1 + { datum baseAddress { - value = "16777216"; + value = "8192"; type = "long"; } } @@ -147,6 +184,14 @@ type = "long"; } } + element onchip_memory2_0.s1 + { + datum baseAddress + { + value = "41951232"; + type = "long"; + } + } element onchip_memory2_0.s2 { datum baseAddress @@ -168,6 +213,32 @@ type = "String"; } } + element sgdma_rx + { + datum _sortIndex + { + value = "11"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } + element sgdma_tx + { + datum _sortIndex + { + value = "12"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } element timer_0 { datum _sortIndex @@ -194,6 +265,19 @@ type = "String"; } } + element triple_speed_ethernet_0 + { + datum _sortIndex + { + value = "10"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } element uart_0 { datum _sortIndex @@ -214,8 +298,8 @@ dionysos_nios2mmu.qpf - - + + @@ -417,6 +501,127 @@ + + + + + + + + {TRANSMIT=sgdma_tx, RECEIVE=sgdma_rx} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/quartus/dionysos_nios2mmu.sopcinfo b/quartus/dionysos_nios2mmu.sopcinfo index a44e48a..eddb46e 100644 --- a/quartus/dionysos_nios2mmu.sopcinfo +++ b/quartus/dionysos_nios2mmu.sopcinfo @@ -4,7 +4,7 @@ kind="com_altera_sopcmodel_ensemble_Ensemble" version="9.1"> - + com.altera.entityinterfaces.moduleext.IDeviceFamily$EDeviceFamily @@ -48,7 +48,7 @@ long - -23323565077 + -64275773308 false true true @@ -56,7 +56,7 @@ long - 1276249234420 + 1276765439648 false true true @@ -239,6 +239,42 @@ parameters are a RESULT of the module parameters. --> clk2 onchip_memory2_0.clk2 + + false + triple_speed_ethernet_0 + receive_clock_connection + triple_speed_ethernet_0.receive_clock_connection + + + false + triple_speed_ethernet_0 + transmit_clock_connection + triple_speed_ethernet_0.transmit_clock_connection + + + false + triple_speed_ethernet_0 + control_port_clock_connection + triple_speed_ethernet_0.control_port_clock_connection + + + false + sgdma_rx + clk + sgdma_rx.clk + + + false + descriptor_memory + clk1 + descriptor_memory.clk1 + + + false + sgdma_tx + clk + sgdma_tx.clk + 41952320 8 + + false + triple_speed_ethernet_0 + control_port + triple_speed_ethernet_0.control_port + 0 + 1024 + + + false + sgdma_rx + csr + sgdma_rx.csr + 1024 + 64 + + + false + sgdma_tx + csr + sgdma_tx.csr + 1088 + 64 + jtag_uart_0.irq 3 + + false + sgdma_rx + csr_irq + sgdma_rx.csr_irq + 4 + + + false + sgdma_tx + csr_irq + sgdma_tx.csr_irq + 5 + - - + + + + embeddedsw.CMacro.TRANSMIT + "sgdma_tx" + + + embeddedsw.CMacro.RECEIVE + "sgdma_rx" + + + embeddedsw.CMacro.TRANSMIT_FIFO_DEPTH + 1024 + + + embeddedsw.CMacro.RECEIVE_FIFO_DEPTH + 1024 + + + embeddedsw.CMacro.FIFO_WIDTH + 32 + + + embeddedsw.CMacro.ENABLE_MACLITE + 0 + + + embeddedsw.CMacro.MACLITE_GIGE + 0 + + + embeddedsw.CMacro.USE_MDIO + 1 + + + embeddedsw.CMacro.NUMBER_OF_CHANNEL + 1 + + + embeddedsw.CMacro.NUMBER_OF_MAC_MDIO_SHARED + 1 + + + embeddedsw.CMacro.IS_MULTICHANNEL_MAC + 0 + + + embeddedsw.CMacro.MDIO_SHARED + 0 + + + embeddedsw.CMacro.REGISTER_SHARED + 0 + + + embeddedsw.CMacro.PCS + 0 + + + embeddedsw.CMacro.PCS_SGMII + 0 + + + embeddedsw.CMacro.PCS_ID + 0u + + + long + 0 + false + true + true + true + + java.lang.String - UNKNOWN + unassigned false true true true - - boolean - false + + long + 0 false true true true - clk_0 - clk - cpu_0 - clk - - - - int - 1 + + java.lang.String + unassigned false true true true - + long - 0x02801000 + 0 false true true true - + java.lang.String - UNKNOWN + unassigned false true true true - - boolean - false + + java.lang.String + {TRANSMIT=sgdma_tx, RECEIVE=sgdma_rx} false true true true - cpu_0 - instruction_master - cpu_0 - jtag_debug_module - - - + int 1 false @@ -8667,50 +8791,47 @@ parameters are a RESULT of the module parameters. --> true true - + + com.altera.megacore.tse.model.IEthernetCoreParameter$eCoreVariation + MAC_ONLY + false + true + true + true + + long - 0x02801000 + 2305 false true true true - - java.lang.String - UNKNOWN + + byte + 0 false true true true - - boolean - false + + int + 8 false true true true - cpu_0 - data_master - cpu_0 - jtag_debug_module - - - - java.lang.String - UNKNOWN + + int + 6 false true true true - + boolean false false @@ -8718,85 +8839,71 @@ parameters are a RESULT of the module parameters. --> true true - clk_0 - clk - sdram_0 - clk - - - + int - 1 + 0 false true true true - + + int + 8 + false + true + true + true + + long - 0x01000000 + 2305 false true true true - java.lang.String - UNKNOWN + com.altera.entityinterfaces.moduleext.IDeviceFamily$EDeviceFamily + CYCLONEIII false true true true - - boolean - false + + int + 10 false true true true - cpu_0 - instruction_master - sdram_0 - s1 - - - + int - 1 - false + 1024 + true true true true - - long - 0x01000000 + + boolean + true false true true true - - java.lang.String - UNKNOWN + + boolean + false false - true + false true true - + boolean false false @@ -8804,26 +8911,15 @@ parameters are a RESULT of the module parameters. --> true true - cpu_0 - data_master - sdram_0 - s1 - - - - java.lang.String - UNKNOWN + + int + 32 false true true true - + boolean false false @@ -8831,17 +8927,6321 @@ parameters are a RESULT of the module parameters. --> true true - clk_0 - clk - tri_state_bridge_0 - clk - - + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.megacore.tse.model.IEthernetCoreParameter$MIIInterface + MII_GMII + false + true + true + true + + + boolean + false + false + false + true + true + + + int + 10 + false + true + true + true + + + int + 1024 + true + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 1 + false + false + true + true + + + int + 20 + false + true + true + true + + + long + 0 + false + false + true + true + + + com.altera.megacore.tse.model.IEthernetCoreParameter$eRamType + AUTO + false + true + true + true + + + byte + 1 + false + true + true + true + + + java.lang.String + dionysos_nios2mmu + true + true + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + timingAdapter + false + true + true + true + + + com.altera.entityinterfaces.moduleext.megawizard.IMegaWizard$EToolContext + SOPC_BUILDER + false + true + true + true + + + com.altera.megacore.tse.model.IEthernetCoreParameter$TransceiverType + GXB + false + false + true + true + + + java.lang.String + 1024 x 32 Bits + true + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + 1024 x 32 Bits + true + true + true + true + + + boolean + false + true + true + true + true + + + boolean + false + true + true + true + true + + + java.lang.String + 0.0 MHz + false + true + true + true + + + boolean + false + true + true + true + true + + + boolean + false + true + true + true + true + + + boolean + false + true + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + receive_clock_connection + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + Prefix,(d4,b3,c2,a1)3,Postfix + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + ff_tx_data + Input + 32 + data + + + ff_tx_eop + Input + 1 + endofpacket + + + ff_tx_err + Input + 1 + error + + + ff_tx_mod + Input + 2 + empty + + + ff_tx_rdy + Output + 1 + ready + + + ff_tx_sop + Input + 1 + startofpacket + + + ff_tx_wren + Input + 1 + valid + + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + ff_tx_clk + Input + 1 + clk + + + + + + java.lang.String + transmit_clock_connection + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + Prefix,(d4,b3,c2,a1)3,Postfix + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + ff_rx_data + Output + 32 + data + + + ff_rx_dval + Output + 1 + valid + + + ff_rx_eop + Output + 1 + endofpacket + + + ff_rx_mod + Output + 2 + empty + + + ff_rx_rdy + Input + 1 + ready + + + ff_rx_sop + Output + 1 + startofpacket + + + rx_err + Output + 6 + error + + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + ff_rx_clk + Input + 1 + clk + + + + + + embeddedsw.configuration.isEthernetMacDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + control_port_clock_connection + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 8 + address + + + readdata + Output + 32 + readdata + + + read + Input + 1 + read + + + writedata + Input + 32 + writedata + + + write + Input + 1 + write + + + waitrequest + Output + 1 + waitrequest + + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + reset + Input + 1 + reset + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + gm_rx_d + Input + 8 + export + + + gm_rx_dv + Input + 1 + export + + + gm_rx_err + Input + 1 + export + + + gm_tx_d + Output + 8 + export + + + gm_tx_en + Output + 1 + export + + + gm_tx_err + Output + 1 + export + + + m_rx_d + Input + 4 + export + + + m_rx_en + Input + 1 + export + + + m_rx_err + Input + 1 + export + + + m_tx_d + Output + 4 + export + + + m_tx_en + Output + 1 + export + + + m_tx_err + Output + 1 + export + + + m_rx_col + Input + 1 + export + + + m_rx_crs + Input + 1 + export + + + tx_clk + Input + 1 + export + + + rx_clk + Input + 1 + export + + + set_10 + Input + 1 + export + + + set_1000 + Input + 1 + export + + + ena_10 + Output + 1 + export + + + eth_mode + Output + 1 + export + + + mdio_out + Output + 1 + export + + + mdio_oen + Output + 1 + export + + + mdio_in + Input + 1 + export + + + mdc + Output + 1 + export + + + + + + + embeddedsw.CMacro.READ_BLOCK_DATA_WIDTH + 32 + + + embeddedsw.CMacro.WRITE_BLOCK_DATA_WIDTH + 32 + + + embeddedsw.CMacro.STREAM_DATA_WIDTH + 32 + + + embeddedsw.CMacro.ADDRESS_WIDTH + 32 + + + embeddedsw.CMacro.HAS_READ_BLOCK + 0 + + + embeddedsw.CMacro.HAS_WRITE_BLOCK + 1 + + + embeddedsw.CMacro.READ_BURSTCOUNT_WIDTH + 4 + + + embeddedsw.CMacro.WRITE_BURSTCOUNT_WIDTH + 4 + + + embeddedsw.CMacro.BURST_TRANSFER + 0 + + + embeddedsw.CMacro.ALWAYS_DO_MAX_BURST + 1 + + + embeddedsw.CMacro.DESCRIPTOR_READ_BURST + 0 + + + embeddedsw.CMacro.UNALIGNED_TRANSFER + 0 + + + embeddedsw.CMacro.CONTROL_SLAVE_DATA_WIDTH + 32 + + + embeddedsw.CMacro.CONTROL_SLAVE_ADDRESS_WIDTH + 4 + + + embeddedsw.CMacro.DESC_DATA_WIDTH + 32 + + + embeddedsw.CMacro.CHAIN_WRITEBACK_DATA_WIDTH + 32 + + + embeddedsw.CMacro.STATUS_TOKEN_DATA_WIDTH + 24 + + + embeddedsw.CMacro.BYTES_TO_TRANSFER_DATA_WIDTH + 16 + + + embeddedsw.CMacro.BURST_DATA_WIDTH + 8 + + + embeddedsw.CMacro.CONTROL_DATA_WIDTH + 8 + + + embeddedsw.CMacro.ATLANTIC_CHANNEL_DATA_WIDTH + 4 + + + embeddedsw.CMacro.COMMAND_FIFO_DATA_WIDTH + 104 + + + embeddedsw.CMacro.SYMBOLS_PER_BEAT + 4 + + + embeddedsw.CMacro.IN_ERROR_WIDTH + 6 + + + embeddedsw.CMacro.OUT_ERROR_WIDTH + 0 + + + int + 64 + true + true + true + true + + + int + 32 + false + true + true + true + + + boolean + true + false + false + true + false + + + int + 2 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 2 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 4 + false + false + true + true + + + int + 6 + false + true + true + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.components.avalon.sgdma.ETransferMode + STREAM_TO_MEMORY + false + true + true + true + + + int + 4 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.affectsTransactionsOnMasters + m_write + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 64 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_chipselect + Input + 1 + chipselect + + + csr_address + Input + 4 + address + + + csr_read + Input + 1 + read + + + csr_write + Input + 1 + write + + + csr_writedata + Input + 32 + writedata + + + csr_readdata + Output + 32 + readdata + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + descriptor_read_readdata + Input + 32 + readdata + + + descriptor_read_readdatavalid + Input + 1 + readdatavalid + + + descriptor_read_waitrequest + Input + 1 + waitrequest + + + descriptor_read_address + Output + 32 + address + + + descriptor_read_read + Output + 1 + read + + + false + descriptor_memory + s1 + descriptor_memory.s1 + 8192 + 8192 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + descriptor_write_waitrequest + Input + 1 + waitrequest + + + descriptor_write_address + Output + 32 + address + + + descriptor_write_write + Output + 1 + write + + + descriptor_write_writedata + Output + 32 + writedata + + + false + descriptor_memory + s1 + descriptor_memory.s1 + 8192 + 8192 + + + + + + com.altera.entityinterfaces.IConnectionPoint + sgdma_rx.csr + false + true + true + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + csr_irq + Output + 1 + irq + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + m_write_waitrequest + Input + 1 + waitrequest + + + m_write_address + Output + 32 + address + + + m_write_write + Output + 1 + write + + + m_write_writedata + Output + 32 + writedata + + + false + sdram_0 + s1 + sdram_0.s1 + 16777216 + 16777216 + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + in_sop + Input + 1 + startofpacket + + + in_eop + Input + 1 + endofpacket + + + in_empty + Input + 2 + empty + + + in_data + Input + 32 + data + + + in_valid + Input + 1 + valid + + + in_ready + Output + 1 + ready + + + in_error + Input + 6 + error + + + + + + + embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE + 0 + + + embeddedsw.CMacro.INIT_CONTENTS_FILE + "descriptor_memory" + + + embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED + 0 + + + embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE + "Automatic" + + + embeddedsw.CMacro.WRITABLE + 1 + + + embeddedsw.CMacro.DUAL_PORT + 0 + + + embeddedsw.CMacro.SIZE_VALUE + 8192u + + + embeddedsw.CMacro.SIZE_MULTIPLE + 1 + + + embeddedsw.CMacro.CONTENTS_INFO + "" + + + embeddedsw.CMacro.RAM_BLOCK_TYPE + "Auto" + + + embeddedsw.CMacro.INIT_MEM_CONTENT + 1 + + + embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR + 0 + + + embeddedsw.CMacro.INSTANCE_ID + "NONE" + + + embeddedsw.CMacro.READ_DURING_WRITE_MODE + "DONT_CARE" + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.HAS_BYTE_LANE + 0 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + QPF_DIR + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonOnchipMemory.AlteraAvalonOnchipMemory$BlockType + AUTO + false + true + true + true + + + int + 32 + false + true + true + true + + + java.lang.String + Cyclone III + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + descriptor_memory + false + false + true + true + + + java.lang.String + NONE + false + false + true + true + + + long + 8192 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonOnchipMemory.AlteraAvalonOnchipMemory$ReadDuringWriteMode + DONT_CARE + false + false + true + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 8192 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk1 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 8192 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 11 + address + + + chipselect + Input + 1 + chipselect + + + clken + Input + 1 + clken + + + readdata + Output + 32 + readdata + + + write + Input + 1 + write + + + writedata + Input + 32 + writedata + + + byteenable + Input + 4 + byteenable + + + + + + + embeddedsw.CMacro.READ_BLOCK_DATA_WIDTH + 32 + + + embeddedsw.CMacro.WRITE_BLOCK_DATA_WIDTH + 32 + + + embeddedsw.CMacro.STREAM_DATA_WIDTH + 32 + + + embeddedsw.CMacro.ADDRESS_WIDTH + 32 + + + embeddedsw.CMacro.HAS_READ_BLOCK + 1 + + + embeddedsw.CMacro.HAS_WRITE_BLOCK + 0 + + + embeddedsw.CMacro.READ_BURSTCOUNT_WIDTH + 4 + + + embeddedsw.CMacro.WRITE_BURSTCOUNT_WIDTH + 4 + + + embeddedsw.CMacro.BURST_TRANSFER + 0 + + + embeddedsw.CMacro.ALWAYS_DO_MAX_BURST + 1 + + + embeddedsw.CMacro.DESCRIPTOR_READ_BURST + 0 + + + embeddedsw.CMacro.UNALIGNED_TRANSFER + 0 + + + embeddedsw.CMacro.CONTROL_SLAVE_DATA_WIDTH + 32 + + + embeddedsw.CMacro.CONTROL_SLAVE_ADDRESS_WIDTH + 4 + + + embeddedsw.CMacro.DESC_DATA_WIDTH + 32 + + + embeddedsw.CMacro.CHAIN_WRITEBACK_DATA_WIDTH + 32 + + + embeddedsw.CMacro.STATUS_TOKEN_DATA_WIDTH + 24 + + + embeddedsw.CMacro.BYTES_TO_TRANSFER_DATA_WIDTH + 16 + + + embeddedsw.CMacro.BURST_DATA_WIDTH + 8 + + + embeddedsw.CMacro.CONTROL_DATA_WIDTH + 8 + + + embeddedsw.CMacro.ATLANTIC_CHANNEL_DATA_WIDTH + 4 + + + embeddedsw.CMacro.COMMAND_FIFO_DATA_WIDTH + 104 + + + embeddedsw.CMacro.SYMBOLS_PER_BEAT + 4 + + + embeddedsw.CMacro.IN_ERROR_WIDTH + 0 + + + embeddedsw.CMacro.OUT_ERROR_WIDTH + 1 + + + int + 64 + true + true + true + true + + + int + 32 + false + true + true + true + + + boolean + true + false + false + true + false + + + int + 2 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 2 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 4 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.sgdma.ETransferMode + MEMORY_TO_STREAM + false + true + true + true + + + int + 4 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.affectsTransactionsOnMasters + m_read + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 64 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + csr_chipselect + Input + 1 + chipselect + + + csr_address + Input + 4 + address + + + csr_read + Input + 1 + read + + + csr_write + Input + 1 + write + + + csr_writedata + Input + 32 + writedata + + + csr_readdata + Output + 32 + readdata + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + descriptor_read_readdata + Input + 32 + readdata + + + descriptor_read_readdatavalid + Input + 1 + readdatavalid + + + descriptor_read_waitrequest + Input + 1 + waitrequest + + + descriptor_read_address + Output + 32 + address + + + descriptor_read_read + Output + 1 + read + + + false + descriptor_memory + s1 + descriptor_memory.s1 + 8192 + 8192 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + descriptor_write_waitrequest + Input + 1 + waitrequest + + + descriptor_write_address + Output + 32 + address + + + descriptor_write_write + Output + 1 + write + + + descriptor_write_writedata + Output + 32 + writedata + + + false + descriptor_memory + s1 + descriptor_memory.s1 + 8192 + 8192 + + + + + + com.altera.entityinterfaces.IConnectionPoint + sgdma_tx.csr + false + true + true + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + csr_irq + Output + 1 + irq + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + m_read_readdata + Input + 32 + readdata + + + m_read_readdatavalid + Input + 1 + readdatavalid + + + m_read_waitrequest + Input + 1 + waitrequest + + + m_read_address + Output + 32 + address + + + m_read_read + Output + 1 + read + + + false + sdram_0 + s1 + sdram_0.s1 + 16777216 + 16777216 + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 4 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + out_data + Output + 32 + data + + + out_valid + Output + 1 + valid + + + out_ready + Input + 1 + ready + + + out_eop + Output + 1 + endofpacket + + + out_sop + Output + 1 + startofpacket + + + out_empty + Output + 2 + empty + + + out_error + Output + 1 + error + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + cpu_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02801000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + instruction_master + cpu_0 + jtag_debug_module + + + + int + 1 + false + true + true + true + + + long + 0x02801000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + cpu_0 + jtag_debug_module + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + sdram_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x01000000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + instruction_master + sdram_0 + s1 + + + + int + 1 + false + true + true + true + + + long + 0x01000000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + sdram_0 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + tri_state_bridge_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x0000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + instruction_master + tri_state_bridge_0 + avalon_slave + + + + int + 1 + false + true + true + true + + + long + 0x0000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + tri_state_bridge_0 + avalon_slave + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + cfi_flash_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02400000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + tri_state_bridge_0 + tristate_master + cfi_flash_0 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + epcs_flash_controller_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02801800 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + instruction_master + epcs_flash_controller_0 + epcs_control_port + + + + int + 1 + false + true + true + true + + + long + 0x02801800 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + epcs_flash_controller_0 + epcs_control_port + + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + d_irq + epcs_flash_controller_0 + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + timer_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02802400 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + timer_0 + s1 + + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + d_irq + timer_0 + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + uart_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02802420 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + uart_0 + s1 + + + + int + 2 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + d_irq + uart_0 + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + jtag_uart_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02802440 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + jtag_uart_0 + avalon_jtag_slave + + + + int + 3 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + d_irq + jtag_uart_0 + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + onchip_memory2_0 + clk1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + onchip_memory2_0 + clk2 + + + start="cpu_0.tightly_coupled_instruction_master_0" + end="onchip_memory2_0.s1"> int 1 @@ -8852,7 +15252,7 @@ parameters are a RESULT of the module parameters. --> long - 0x0000 + 0x02802000 false true true @@ -8875,16 +15275,16 @@ parameters are a RESULT of the module parameters. --> true cpu_0 - instruction_master - tri_state_bridge_0 - avalon_slave + tightly_coupled_instruction_master_0 + onchip_memory2_0 + s1 + start="cpu_0.tightly_coupled_data_master_0" + end="onchip_memory2_0.s2"> int 1 @@ -8895,7 +15295,7 @@ parameters are a RESULT of the module parameters. --> long - 0x0000 + 0x02802000 false true true @@ -8918,16 +15318,16 @@ parameters are a RESULT of the module parameters. --> true cpu_0 - data_master - tri_state_bridge_0 - avalon_slave + tightly_coupled_data_master_0 + onchip_memory2_0 + s2 + end="triple_speed_ethernet_0.receive_clock_connection"> java.lang.String UNKNOWN @@ -8946,15 +15346,42 @@ parameters are a RESULT of the module parameters. --> clk_0 clk - cfi_flash_0 - clk + triple_speed_ethernet_0 + receive_clock_connection + start="clk_0.clk" + end="triple_speed_ethernet_0.transmit_clock_connection"> + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + triple_speed_ethernet_0 + transmit_clock_connection + + int 1 @@ -8965,7 +15392,7 @@ parameters are a RESULT of the module parameters. --> long - 0x02400000 + 0x0000 false true true @@ -8987,17 +15414,17 @@ parameters are a RESULT of the module parameters. --> true true - tri_state_bridge_0 - tristate_master - cfi_flash_0 - s1 + cpu_0 + data_master + triple_speed_ethernet_0 + control_port + end="triple_speed_ethernet_0.control_port_clock_connection"> java.lang.String UNKNOWN @@ -9016,31 +15443,15 @@ parameters are a RESULT of the module parameters. --> clk_0 clk - epcs_flash_controller_0 - clk + triple_speed_ethernet_0 + control_port_clock_connection - - int - 1 - false - true - true - true - - - long - 0x02801800 - false - true - true - true - + name="clk_0.clk/sgdma_rx.clk" + kind="clock" + version="9.1" + start="clk_0.clk" + end="sgdma_rx.clk"> java.lang.String UNKNOWN @@ -9057,17 +15468,17 @@ parameters are a RESULT of the module parameters. --> true true - cpu_0 - instruction_master - epcs_flash_controller_0 - epcs_control_port + clk_0 + clk + sgdma_rx + clk + end="sgdma_rx.csr"> int 1 @@ -9078,7 +15489,7 @@ parameters are a RESULT of the module parameters. --> long - 0x02801800 + 0x0400 false true true @@ -9102,18 +15513,18 @@ parameters are a RESULT of the module parameters. --> cpu_0 data_master - epcs_flash_controller_0 - epcs_control_port + sgdma_rx + csr + end="sgdma_rx.csr_irq"> int - 1 + 4 false true true @@ -9137,15 +15548,15 @@ parameters are a RESULT of the module parameters. --> cpu_0 d_irq - epcs_flash_controller_0 - irq + sgdma_rx + csr_irq + end="descriptor_memory.clk1"> java.lang.String UNKNOWN @@ -9164,15 +15575,42 @@ parameters are a RESULT of the module parameters. --> clk_0 clk - timer_0 + descriptor_memory + clk1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + sgdma_tx clk + end="sgdma_tx.csr"> int 1 @@ -9183,7 +15621,7 @@ parameters are a RESULT of the module parameters. --> long - 0x02802400 + 0x0440 false true true @@ -9207,18 +15645,18 @@ parameters are a RESULT of the module parameters. --> cpu_0 data_master - timer_0 - s1 + sgdma_tx + csr + end="sgdma_tx.csr_irq"> int - 0 + 5 false true true @@ -9242,42 +15680,15 @@ parameters are a RESULT of the module parameters. --> cpu_0 d_irq - timer_0 - irq - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - uart_0 - clk + sgdma_tx + csr_irq + start="sgdma_rx.descriptor_read" + end="descriptor_memory.s1"> int 1 @@ -9288,7 +15699,7 @@ parameters are a RESULT of the module parameters. --> long - 0x02802420 + 0x2000 false true true @@ -9310,52 +15721,33 @@ parameters are a RESULT of the module parameters. --> true true - cpu_0 - data_master - uart_0 + sgdma_rx + descriptor_read + descriptor_memory s1 - - int - 2 - false - true - true - true - - - java.lang.String - UNKNOWN + name="sgdma_rx.descriptor_write/descriptor_memory.s1" + kind="avalon" + version="6.1" + start="sgdma_rx.descriptor_write" + end="descriptor_memory.s1"> + + int + 1 false true true true - - boolean - false + + long + 0x2000 false true true true - cpu_0 - d_irq - uart_0 - irq - - java.lang.String UNKNOWN @@ -9372,17 +15764,17 @@ parameters are a RESULT of the module parameters. --> true true - clk_0 - clk - jtag_uart_0 - clk + sgdma_rx + descriptor_write + descriptor_memory + s1 + start="sgdma_rx.m_write" + end="sdram_0.s1"> int 1 @@ -9393,7 +15785,7 @@ parameters are a RESULT of the module parameters. --> long - 0x02802440 + 0x01000000 false true true @@ -9415,25 +15807,17 @@ parameters are a RESULT of the module parameters. --> true true - cpu_0 - data_master - jtag_uart_0 - avalon_jtag_slave + sgdma_rx + m_write + sdram_0 + s1 - - int - 3 - false - true - true - true - + start="triple_speed_ethernet_0.receive" + end="sgdma_rx.in"> java.lang.String UNKNOWN @@ -9450,17 +15834,17 @@ parameters are a RESULT of the module parameters. --> true true - cpu_0 - d_irq - jtag_uart_0 - irq + triple_speed_ethernet_0 + receive + sgdma_rx + in + start="sgdma_tx.out" + end="triple_speed_ethernet_0.transmit"> java.lang.String UNKNOWN @@ -9477,17 +15861,33 @@ parameters are a RESULT of the module parameters. --> true true - clk_0 - clk - onchip_memory2_0 - clk1 + sgdma_tx + out + triple_speed_ethernet_0 + transmit + name="sgdma_tx.m_read/sdram_0.s1" + kind="avalon" + version="6.1" + start="sgdma_tx.m_read" + end="sdram_0.s1"> + + int + 1 + false + true + true + true + + + long + 0x01000000 + false + true + true + true + java.lang.String UNKNOWN @@ -9504,17 +15904,17 @@ parameters are a RESULT of the module parameters. --> true true - clk_0 - clk - onchip_memory2_0 - clk2 + sgdma_tx + m_read + sdram_0 + s1 + start="sgdma_tx.descriptor_read" + end="descriptor_memory.s1"> int 1 @@ -9525,7 +15925,7 @@ parameters are a RESULT of the module parameters. --> long - 0x02802000 + 0x2000 false true true @@ -9547,17 +15947,17 @@ parameters are a RESULT of the module parameters. --> true true - cpu_0 - tightly_coupled_instruction_master_0 - onchip_memory2_0 + sgdma_tx + descriptor_read + descriptor_memory s1 + start="sgdma_tx.descriptor_write" + end="descriptor_memory.s1"> int 1 @@ -9568,7 +15968,7 @@ parameters are a RESULT of the module parameters. --> long - 0x02802000 + 0x2000 false true true @@ -9590,33 +15990,57 @@ parameters are a RESULT of the module parameters. --> true true - cpu_0 - tightly_coupled_data_master_0 - onchip_memory2_0 - s2 + sgdma_tx + descriptor_write + descriptor_memory + s1 - 1 - clock_source + 10 + avalon_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output + Avalon Memory Mapped Master 9.1 1 - altera_avalon_epcs_flash_controller + altera_avalon_cfi_flash com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - EPCS Serial Flash Controller + Flash Memory Interface (CFI) 9.1 1 - avalon_tristate_slave + altera_avalon_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + UART (RS-232 Serial Port) + 9.1 + + + 1 + avalon_tristate_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Tristate Slave + Avalon Memory Mapped Tristate Master + 9.1 + + + 1 + triple_speed_ethernet + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Triple-Speed Ethernet + 9.1 + + + 1 + altera_nios2 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Nios II Processor 9.1 @@ -9628,35 +16052,43 @@ parameters are a RESULT of the module parameters. --> 9.1 - 3 - conduit + 6 + interrupt com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit Endpoint - 7.1 + com.altera.entityinterfaces.IConnection + Interrupt Connection + 9.1 1 - altera_avalon_jtag_uart + altera_avalon_timer com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - JTAG UART + Interval Timer 9.1 13 - avalon + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 9.1 + + + 2 + avalon_streaming com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Connection - 6.1 + Avalon Streaming Connection + 9.1 - 11 - clock_sink + 16 + clock com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input + com.altera.entityinterfaces.IConnection + Clock Connection 9.1 @@ -9668,125 +16100,133 @@ parameters are a RESULT of the module parameters. --> 9.1 - 10 - clock + 22 + avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection - Clock Connection + Avalon Memory Mapped Connection + 6.1 + + + 2 + altera_avalon_sgdma + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Scatter-Gather DMA Controller 9.1 1 - avalon_tristate_master + altera_avalon_jtag_uart com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Tristate Master + com.altera.entityinterfaces.IModule + JTAG UART 9.1 1 - altera_avalon_cfi_flash + altera_avalon_tri_state_bridge com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Flash Memory Interface (CFI) + Avalon-MM Tristate Bridge 9.1 - 4 - avalon_master + 1 + nios_custom_instruction_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Master + Custom Instruction Master 9.1 1 - altera_nios2 + clock_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Nios II Processor + Clock Source 9.1 - 1 - nios_custom_instruction_master + 6 + interrupt_sender com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Custom Instruction Master + Interrupt Sender 9.1 - 1 - avalon_tristate + 17 + clock_sink com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Tristate Connection + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input 9.1 - 1 - clock_source + 2 + altera_avalon_onchip_memory2 com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Clock Source + On-Chip Memory (RAM or ROM) 9.1 - 1 - altera_avalon_timer + 2 + avalon_streaming_sink com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Interval Timer + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Sink 9.1 1 - altera_avalon_tri_state_bridge + avalon_tristate com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Avalon-MM Tristate Bridge + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Tristate Connection 9.1 - 9 - avalon_slave + 4 + conduit com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Slave - 9.1 + Conduit Endpoint + 7.1 1 - altera_avalon_uart + altera_avalon_epcs_flash_controller com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - UART (RS-232 Serial Port) + EPCS Serial Flash Controller 9.1 - 4 - interrupt + 2 + avalon_streaming_source com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Interrupt Connection + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source 9.1 1 - altera_avalon_onchip_memory2 + avalon_tristate_slave com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - On-Chip Memory (RAM or ROM) + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Tristate Slave 9.1 - 4 - interrupt_sender + 1 + clock_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Sender + Clock Output 9.1 9.1sp2 350 - 0023AE674DE0000001292660CE4E + 0023AE674DE000000129451D90C8 -- cgit v1.2.3-54-g00ecf