From 267b9022dd49d0d4a2ee88044e8ff734d139a282 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Wed, 19 Jan 2011 17:21:56 +0100 Subject: Updates: Pull LEDS low, rename TSE MAC, add watchdog timer, add sysid --- .gitignore | 11 + dionysos_top.vhd | 96 +- quartus/dionysos_nios2mmu.bsf | 262 ++--- quartus/dionysos_nios2mmu.qsf | 18 +- quartus/dionysos_nios2mmu.sopc | 257 ++++- quartus/dionysos_nios2mmu.sopcinfo | 1978 +++++++++++++++++++++++++++++------- 6 files changed, 2030 insertions(+), 592 deletions(-) diff --git a/.gitignore b/.gitignore index f0fb01b..5299300 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,12 @@ +quartus/db/ +quartus/incremental_db/ +quartus/dionysos_nios2mmu_sim/ quartus/.sopc_builder +quartus/*.bak +quartus/*.html +quartus/*.summary + +# VHDL created by SOPC builder +quartus/cpu_0* +quartus/tse_mac*.vhd +quartus/watchdog_timer.vhd diff --git a/dionysos_top.vhd b/dionysos_top.vhd index 66e0392..6924a30 100644 --- a/dionysos_top.vhd +++ b/dionysos_top.vhd @@ -6,9 +6,10 @@ -- _| |_| | | | |____ ____) | (University of Applied Sciences) - -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - ------------------------------------------------------------------ --- $LastChangedDate: 2008-02-06 14:28:53 +0100 (Mi, 06 Feb 2008) $ --- $Rev: 828 $ --- $Author: ffar $ +-- +-- $LastChangedDate: $ +-- $Rev: $ +-- $Author: $ ----------------------------------------------------------------- -- -- Change History @@ -200,6 +201,17 @@ architecture rtl of dionysos_top is --! FPGA main clock frequency (50MHz) constant C_FPGA_FREQ : integer := 50000000; + --! front pannel LEDs + signal leds : std_logic_vector(15 downto 0); + + --! @name SDRAM Data + --@{ + --! Nios SDRAM controller data mask (byte select) + signal dram_dqm : std_logic_vector(1 downto 0); + --! Nios SDRAM controller bank address + signal dram_ba : std_logic_vector(1 downto 0); + --@} + --! 50 MHz Clock which is Source Synchronous to the DRAM Data signal pll_clk_50 : std_logic; --! 25 MHz Clock @@ -214,16 +226,6 @@ architecture rtl of dionysos_top is signal fpga_reset_n_ff_100 : std_logic; --! Reset for the NIOS. Active in Ethernet Modus (no DSL) signal reset_nios_n : std_logic; - - --! front pannel LEDs - signal leds : std_logic_vector(15 downto 0); - - --! @name SDRAM Data - --@{ - --! Nios SDRAM controller data mask (byte select) - signal dram_dqm : std_logic_vector(1 downto 0); - --! Nios SDRAM controller bank address - signal dram_ba : std_logic_vector(1 downto 0); --@} --! @name RX byte stream interface of ethernet phy 1 @@ -263,7 +265,7 @@ architecture rtl of dionysos_top is signal et_phy2_tx_ack_2 : std_logic; --@} - --! link status of ethernet interfaces (from MDIO) \todo tidy mdio + --! link status of ethernet interfaces (from MDIO) signal et_phy1_link_status : std_logic_vector(3 downto 0); --! synchronised on clock dip switch states @@ -356,6 +358,11 @@ architecture rtl of dionysos_top is reset_n_o => fpga_reset_n_ff_100 -- reset 100 clocks delayed ); + gen_led_g_o <= (others => '1'); + gen_led_r_o <= (others => '1'); + + gp_led_o <= (others => '1'); + -- NIOSII CPU flash_reset_n_o <= '1'; fash_acc_o <= '0'; -- Hardware Write Protect input (accelerated program operations) @@ -408,30 +415,31 @@ architecture rtl of dionysos_top is sdo_from_the_epcs_flash_controller_0 => config_asd0_o, -- TSE MAC - -- ena_10_from_the_triple_speed_ethernet_0 => ena_10_from_the_triple_speed_ethernet_0, - -- eth_mode_from_the_triple_speed_ethernet_0 => eth_mode_from_the_triple_speed_ethernet_0, - gm_rx_d_to_the_triple_speed_ethernet_0 => (others => '0'), - gm_rx_dv_to_the_triple_speed_ethernet_0 => '0', - gm_rx_err_to_the_triple_speed_ethernet_0 => '0', - -- gm_tx_d_from_the_triple_speed_ethernet_0 => gm_tx_d_from_the_triple_speed_ethernet_0, - -- gm_tx_en_from_the_triple_speed_ethernet_0 => gm_tx_en_from_the_triple_speed_ethernet_0, - -- gm_tx_err_from_the_triple_speed_ethernet_0 => gm_tx_err_from_the_triple_speed_ethernet_0, - m_rx_col_to_the_triple_speed_ethernet_0 => et_phy2_col_1_i, - m_rx_crs_to_the_triple_speed_ethernet_0 => '1', -- et_phy2_crs_1_i is not the same in rmii mode - m_rx_d_to_the_triple_speed_ethernet_0 => mii_rxd_to_mac_0, - m_rx_en_to_the_triple_speed_ethernet_0 => mii_rx_dv_to_mac_0, - m_rx_err_to_the_triple_speed_ethernet_0 => '0', - mdio_in_to_the_triple_speed_ethernet_0 => mac_mdio_in, - m_tx_d_from_the_triple_speed_ethernet_0 => mii_txd_from_mac_0, - m_tx_en_from_the_triple_speed_ethernet_0 => mii_tx_en_from_mac_0, - -- m_tx_err_from_the_triple_speed_ethernet_0 => m_tx_err_from_the_triple_speed_ethernet_0, - mdc_from_the_triple_speed_ethernet_0 => et_phy2_mdc_o, - mdio_oen_from_the_triple_speed_ethernet_0 => mac_mdio_en_n, - mdio_out_from_the_triple_speed_ethernet_0 => mac_mdio_out, - rx_clk_to_the_triple_speed_ethernet_0 => pll_clk_25, - set_1000_to_the_triple_speed_ethernet_0 => '0', -- tie to 0 if not used - set_10_to_the_triple_speed_ethernet_0 => '0', -- tie to 0 if not used - tx_clk_to_the_triple_speed_ethernet_0 => pll_clk_25 + -- ena_10_from_the_tse_mac => ena_10_from_the_tse_mac, + -- eth_mode_from_the_tse_mac => eth_mode_from_the_tse_mac, + gm_rx_d_to_the_tse_mac => (others => '0'), + gm_rx_dv_to_the_tse_mac => '0', + gm_rx_err_to_the_tse_mac => '0', + -- gm_tx_d_from_the_tse_mac => gm_tx_d_from_the_tse_mac, + -- gm_tx_en_from_the_tse_mac => gm_tx_en_from_the_tse_mac, + -- gm_tx_err_from_the_tse_mac => gm_tx_err_from_the_tse_mac, + m_rx_col_to_the_tse_mac => et_phy2_col_1_i, + m_rx_crs_to_the_tse_mac => '1', -- et_phy2_crs_1_i is not the same in rmii mode + m_rx_d_to_the_tse_mac => mii_rxd_to_mac_0, + m_rx_en_to_the_tse_mac => mii_rx_dv_to_mac_0, + m_rx_err_to_the_tse_mac => '0', + + m_tx_d_from_the_tse_mac => mii_txd_from_mac_0, + m_tx_en_from_the_tse_mac => mii_tx_en_from_mac_0, + -- m_tx_err_from_the_tse_mac => m_tx_err_from_the_tse_mac, + mdio_in_to_the_tse_mac => mac_mdio_in, + mdc_from_the_tse_mac => et_phy2_mdc_o, + mdio_oen_from_the_tse_mac => mac_mdio_en_n, + mdio_out_from_the_tse_mac => mac_mdio_out, + rx_clk_to_the_tse_mac => pll_clk_25, + set_1000_to_the_tse_mac => '0', -- tie to 0 if not used + set_10_to_the_tse_mac => '0', -- tie to 0 if not used + tx_clk_to_the_tse_mac => pll_clk_25 ); --------------------------------------------------------------------- @@ -459,8 +467,8 @@ architecture rtl of dionysos_top is reset_n_i => reset_n, clk_25_i => pll_clk_25, clk_50_i => pll_clk_50, - rmii_crs_i => et_phy2_crs_1_i, - + rmii_link_i => '1', -- et_phy2_crs_1_i is not the same in RMII mode + -- Transmit Path mii_tx_en_i => mii_tx_en_from_mac_0, mii_txd_i => mii_txd_from_mac_0, @@ -472,7 +480,7 @@ architecture rtl of dionysos_top is rmii_rxd_i => et_phy2_rxd_1_i(1 downto 0), mii_rx_dv_o => mii_rx_dv_to_mac_0, - mii_rxd_o => mii_rxd_to_mac_0 + mii_rxd_o => mii_rxd_to_mac_0 ); et_phy2_txd_2_o(3 downto 2) <= "00"; @@ -482,8 +490,8 @@ architecture rtl of dionysos_top is reset_n_i => reset_n, clk_25_i => pll_clk_25, clk_50_i => pll_clk_50, - rmii_crs_i => et_phy2_crs_2_i, - + rmii_link_i => '1', -- et_phy2_crs_2_i is not the same in RMII mode + -- Transmit Path mii_tx_en_i => mii_tx_en_from_mac_1, mii_txd_i => mii_txd_from_mac_1, @@ -495,7 +503,7 @@ architecture rtl of dionysos_top is rmii_rxd_i => et_phy2_rxd_2_i(1 downto 0), mii_rx_dv_o => mii_rx_dv_to_mac_1, - mii_rxd_o => mii_rxd_to_mac_1 + mii_rxd_o => mii_rxd_to_mac_1 ); ------------------------------------------------------------------------ diff --git a/quartus/dionysos_nios2mmu.bsf b/quartus/dionysos_nios2mmu.bsf index 64435b0..225bc4f 100644 --- a/quartus/dionysos_nios2mmu.bsf +++ b/quartus/dionysos_nios2mmu.bsf @@ -1,6 +1,6 @@ (header "symbol" (version "1.1")) (symbol -(rect 0 0 528 656) +(rect 0 0 448 656) (text "dionysos_nios2mmu" (rect 4 0 136 16)(font "Arial" (font_size 10))) (text "inst" (rect 4 640 28 656)(font "Arial")) (port @@ -27,92 +27,92 @@ (port (pt 0 400) (input) -(text "gm_rx_d_to_the_triple_speed_ethernet_0[7..0] " (rect 0 0 225 16)(font "Arial" (font_size 8))) -(text "gm_rx_d_to_the_triple_speed_ethernet_0[7..0] " (rect 20 393 245 409)(font "Arial" (font_size 8))) +(text "gm_rx_d_to_the_tse_mac[7..0] " (rect 0 0 149 16)(font "Arial" (font_size 8))) +(text "gm_rx_d_to_the_tse_mac[7..0] " (rect 20 393 169 409)(font "Arial" (font_size 8))) (line (pt 0 400)(pt 16 400)(line_width 3)) ) (port (pt 0 416) (input) -(text "gm_rx_dv_to_the_triple_speed_ethernet_0 " (rect 0 0 206 16)(font "Arial" (font_size 8))) -(text "gm_rx_dv_to_the_triple_speed_ethernet_0 " (rect 20 409 226 425)(font "Arial" (font_size 8))) +(text "gm_rx_dv_to_the_tse_mac " (rect 0 0 130 16)(font "Arial" (font_size 8))) +(text "gm_rx_dv_to_the_tse_mac " (rect 20 409 150 425)(font "Arial" (font_size 8))) (line (pt 0 416)(pt 16 416)(line_width 1)) ) (port (pt 0 432) (input) -(text "gm_rx_err_to_the_triple_speed_ethernet_0 " (rect 0 0 208 16)(font "Arial" (font_size 8))) -(text "gm_rx_err_to_the_triple_speed_ethernet_0 " (rect 20 425 228 441)(font "Arial" (font_size 8))) +(text "gm_rx_err_to_the_tse_mac " (rect 0 0 132 16)(font "Arial" (font_size 8))) +(text "gm_rx_err_to_the_tse_mac " (rect 20 425 152 441)(font "Arial" (font_size 8))) (line (pt 0 432)(pt 16 432)(line_width 1)) ) (port (pt 0 448) (input) -(text "m_rx_col_to_the_triple_speed_ethernet_0 " (rect 0 0 203 16)(font "Arial" (font_size 8))) -(text "m_rx_col_to_the_triple_speed_ethernet_0 " (rect 20 441 223 457)(font "Arial" (font_size 8))) +(text "m_rx_col_to_the_tse_mac " (rect 0 0 127 16)(font "Arial" (font_size 8))) +(text "m_rx_col_to_the_tse_mac " (rect 20 441 147 457)(font "Arial" (font_size 8))) (line (pt 0 448)(pt 16 448)(line_width 1)) ) (port (pt 0 464) (input) -(text "m_rx_crs_to_the_triple_speed_ethernet_0 " (rect 0 0 203 16)(font "Arial" (font_size 8))) -(text "m_rx_crs_to_the_triple_speed_ethernet_0 " (rect 20 457 223 473)(font "Arial" (font_size 8))) +(text "m_rx_crs_to_the_tse_mac " (rect 0 0 127 16)(font "Arial" (font_size 8))) +(text "m_rx_crs_to_the_tse_mac " (rect 20 457 148 473)(font "Arial" (font_size 8))) (line (pt 0 464)(pt 16 464)(line_width 1)) ) (port (pt 0 480) (input) -(text "m_rx_d_to_the_triple_speed_ethernet_0[3..0] " (rect 0 0 219 16)(font "Arial" (font_size 8))) -(text "m_rx_d_to_the_triple_speed_ethernet_0[3..0] " (rect 20 473 239 489)(font "Arial" (font_size 8))) +(text "m_rx_d_to_the_tse_mac[3..0] " (rect 0 0 143 16)(font "Arial" (font_size 8))) +(text "m_rx_d_to_the_tse_mac[3..0] " (rect 20 473 163 489)(font "Arial" (font_size 8))) (line (pt 0 480)(pt 16 480)(line_width 3)) ) (port (pt 0 496) (input) -(text "m_rx_en_to_the_triple_speed_ethernet_0 " (rect 0 0 201 16)(font "Arial" (font_size 8))) -(text "m_rx_en_to_the_triple_speed_ethernet_0 " (rect 20 489 221 505)(font "Arial" (font_size 8))) +(text "m_rx_en_to_the_tse_mac " (rect 0 0 125 16)(font "Arial" (font_size 8))) +(text "m_rx_en_to_the_tse_mac " (rect 20 489 145 505)(font "Arial" (font_size 8))) (line (pt 0 496)(pt 16 496)(line_width 1)) ) (port (pt 0 512) (input) -(text "m_rx_err_to_the_triple_speed_ethernet_0 " (rect 0 0 202 16)(font "Arial" (font_size 8))) -(text "m_rx_err_to_the_triple_speed_ethernet_0 " (rect 20 505 222 521)(font "Arial" (font_size 8))) +(text "m_rx_err_to_the_tse_mac " (rect 0 0 126 16)(font "Arial" (font_size 8))) +(text "m_rx_err_to_the_tse_mac " (rect 20 505 146 521)(font "Arial" (font_size 8))) (line (pt 0 512)(pt 16 512)(line_width 1)) ) (port (pt 0 528) (input) -(text "mdio_in_to_the_triple_speed_ethernet_0 " (rect 0 0 198 16)(font "Arial" (font_size 8))) -(text "mdio_in_to_the_triple_speed_ethernet_0 " (rect 20 521 218 537)(font "Arial" (font_size 8))) +(text "mdio_in_to_the_tse_mac " (rect 0 0 122 16)(font "Arial" (font_size 8))) +(text "mdio_in_to_the_tse_mac " (rect 20 521 142 537)(font "Arial" (font_size 8))) (line (pt 0 528)(pt 16 528)(line_width 1)) ) (port (pt 0 544) (input) -(text "rx_clk_to_the_triple_speed_ethernet_0 " (rect 0 0 187 16)(font "Arial" (font_size 8))) -(text "rx_clk_to_the_triple_speed_ethernet_0 " (rect 20 537 207 553)(font "Arial" (font_size 8))) +(text "rx_clk_to_the_tse_mac " (rect 0 0 111 16)(font "Arial" (font_size 8))) +(text "rx_clk_to_the_tse_mac " (rect 20 537 131 553)(font "Arial" (font_size 8))) (line (pt 0 544)(pt 16 544)(line_width 1)) ) (port (pt 0 560) (input) -(text "set_1000_to_the_triple_speed_ethernet_0 " (rect 0 0 205 16)(font "Arial" (font_size 8))) -(text "set_1000_to_the_triple_speed_ethernet_0 " (rect 20 553 225 569)(font "Arial" (font_size 8))) +(text "set_1000_to_the_tse_mac " (rect 0 0 129 16)(font "Arial" (font_size 8))) +(text "set_1000_to_the_tse_mac " (rect 20 553 149 569)(font "Arial" (font_size 8))) (line (pt 0 560)(pt 16 560)(line_width 1)) ) (port (pt 0 576) (input) -(text "set_10_to_the_triple_speed_ethernet_0 " (rect 0 0 192 16)(font "Arial" (font_size 8))) -(text "set_10_to_the_triple_speed_ethernet_0 " (rect 20 569 212 585)(font "Arial" (font_size 8))) +(text "set_10_to_the_tse_mac " (rect 0 0 117 16)(font "Arial" (font_size 8))) +(text "set_10_to_the_tse_mac " (rect 20 569 137 585)(font "Arial" (font_size 8))) (line (pt 0 576)(pt 16 576)(line_width 1)) ) (port (pt 0 592) (input) -(text "tx_clk_to_the_triple_speed_ethernet_0 " (rect 0 0 186 16)(font "Arial" (font_size 8))) -(text "tx_clk_to_the_triple_speed_ethernet_0 " (rect 20 585 206 601)(font "Arial" (font_size 8))) +(text "tx_clk_to_the_tse_mac " (rect 0 0 110 16)(font "Arial" (font_size 8))) +(text "tx_clk_to_the_tse_mac " (rect 20 585 130 601)(font "Arial" (font_size 8))) (line (pt 0 592)(pt 16 592)(line_width 1)) ) (port @@ -123,213 +123,213 @@ (line (pt 0 624)(pt 16 624)(line_width 1)) ) (port -(pt 528 80) +(pt 448 80) (output) (text "dclk_from_the_epcs_flash_controller_0 " (rect 0 0 188 16)(font "Arial" (font_size 8))) -(text "dclk_from_the_epcs_flash_controller_0 " (rect 313 73 501 89)(font "Arial" (font_size 8))) -(line (pt 512 80)(pt 528 80)(line_width 1)) +(text "dclk_from_the_epcs_flash_controller_0 " (rect 233 73 421 89)(font "Arial" (font_size 8))) +(line (pt 432 80)(pt 448 80)(line_width 1)) ) (port -(pt 528 96) +(pt 448 96) (output) (text "sce_from_the_epcs_flash_controller_0 " (rect 0 0 186 16)(font "Arial" (font_size 8))) -(text "sce_from_the_epcs_flash_controller_0 " (rect 315 89 501 105)(font "Arial" (font_size 8))) -(line (pt 512 96)(pt 528 96)(line_width 1)) +(text "sce_from_the_epcs_flash_controller_0 " (rect 235 89 421 105)(font "Arial" (font_size 8))) +(line (pt 432 96)(pt 448 96)(line_width 1)) ) (port -(pt 528 112) +(pt 448 112) (output) (text "sdo_from_the_epcs_flash_controller_0 " (rect 0 0 186 16)(font "Arial" (font_size 8))) -(text "sdo_from_the_epcs_flash_controller_0 " (rect 314 105 501 121)(font "Arial" (font_size 8))) -(line (pt 512 112)(pt 528 112)(line_width 1)) +(text "sdo_from_the_epcs_flash_controller_0 " (rect 234 105 421 121)(font "Arial" (font_size 8))) +(line (pt 432 112)(pt 448 112)(line_width 1)) ) (port -(pt 528 144) +(pt 448 144) (output) (text "zs_addr_from_the_sdram_0[11..0] " (rect 0 0 165 16)(font "Arial" (font_size 8))) -(text "zs_addr_from_the_sdram_0[11..0] " (rect 335 137 501 153)(font "Arial" (font_size 8))) -(line (pt 512 144)(pt 528 144)(line_width 3)) +(text "zs_addr_from_the_sdram_0[11..0] " (rect 255 137 421 153)(font "Arial" (font_size 8))) +(line (pt 432 144)(pt 448 144)(line_width 3)) ) (port -(pt 528 160) +(pt 448 160) (output) (text "zs_ba_from_the_sdram_0[1..0] " (rect 0 0 150 16)(font "Arial" (font_size 8))) -(text "zs_ba_from_the_sdram_0[1..0] " (rect 351 153 501 169)(font "Arial" (font_size 8))) -(line (pt 512 160)(pt 528 160)(line_width 3)) +(text "zs_ba_from_the_sdram_0[1..0] " (rect 271 153 421 169)(font "Arial" (font_size 8))) +(line (pt 432 160)(pt 448 160)(line_width 3)) ) (port -(pt 528 176) +(pt 448 176) (output) (text "zs_cas_n_from_the_sdram_0 " (rect 0 0 143 16)(font "Arial" (font_size 8))) -(text "zs_cas_n_from_the_sdram_0 " (rect 358 169 501 185)(font "Arial" (font_size 8))) -(line (pt 512 176)(pt 528 176)(line_width 1)) +(text "zs_cas_n_from_the_sdram_0 " (rect 278 169 421 185)(font "Arial" (font_size 8))) +(line (pt 432 176)(pt 448 176)(line_width 1)) ) (port -(pt 528 192) +(pt 448 192) (output) (text "zs_cke_from_the_sdram_0 " (rect 0 0 131 16)(font "Arial" (font_size 8))) -(text "zs_cke_from_the_sdram_0 " (rect 370 185 501 201)(font "Arial" (font_size 8))) -(line (pt 512 192)(pt 528 192)(line_width 1)) +(text "zs_cke_from_the_sdram_0 " (rect 290 185 421 201)(font "Arial" (font_size 8))) +(line (pt 432 192)(pt 448 192)(line_width 1)) ) (port -(pt 528 208) +(pt 448 208) (output) (text "zs_cs_n_from_the_sdram_0 " (rect 0 0 137 16)(font "Arial" (font_size 8))) -(text "zs_cs_n_from_the_sdram_0 " (rect 364 201 501 217)(font "Arial" (font_size 8))) -(line (pt 512 208)(pt 528 208)(line_width 1)) +(text "zs_cs_n_from_the_sdram_0 " (rect 284 201 421 217)(font "Arial" (font_size 8))) +(line (pt 432 208)(pt 448 208)(line_width 1)) ) (port -(pt 528 224) +(pt 448 224) (bidir) (text "zs_dq_to_and_from_the_sdram_0[15..0] " (rect 0 0 195 16)(font "Arial" (font_size 8))) -(text "zs_dq_to_and_from_the_sdram_0[15..0] " (rect 306 217 501 233)(font "Arial" (font_size 8))) -(line (pt 512 224)(pt 528 224)(line_width 3)) +(text "zs_dq_to_and_from_the_sdram_0[15..0] " (rect 226 217 421 233)(font "Arial" (font_size 8))) +(line (pt 432 224)(pt 448 224)(line_width 3)) ) (port -(pt 528 240) +(pt 448 240) (output) (text "zs_dqm_from_the_sdram_0[1..0] " (rect 0 0 159 16)(font "Arial" (font_size 8))) -(text "zs_dqm_from_the_sdram_0[1..0] " (rect 342 233 501 249)(font "Arial" (font_size 8))) -(line (pt 512 240)(pt 528 240)(line_width 3)) +(text "zs_dqm_from_the_sdram_0[1..0] " (rect 262 233 421 249)(font "Arial" (font_size 8))) +(line (pt 432 240)(pt 448 240)(line_width 3)) ) (port -(pt 528 256) +(pt 448 256) (output) (text "zs_ras_n_from_the_sdram_0 " (rect 0 0 141 16)(font "Arial" (font_size 8))) -(text "zs_ras_n_from_the_sdram_0 " (rect 360 249 501 265)(font "Arial" (font_size 8))) -(line (pt 512 256)(pt 528 256)(line_width 1)) +(text "zs_ras_n_from_the_sdram_0 " (rect 280 249 421 265)(font "Arial" (font_size 8))) +(line (pt 432 256)(pt 448 256)(line_width 1)) ) (port -(pt 528 272) +(pt 448 272) (output) (text "zs_we_n_from_the_sdram_0 " (rect 0 0 139 16)(font "Arial" (font_size 8))) -(text "zs_we_n_from_the_sdram_0 " (rect 362 265 501 281)(font "Arial" (font_size 8))) -(line (pt 512 272)(pt 528 272)(line_width 1)) +(text "zs_we_n_from_the_sdram_0 " (rect 282 265 421 281)(font "Arial" (font_size 8))) +(line (pt 432 272)(pt 448 272)(line_width 1)) ) (port -(pt 528 304) +(pt 448 304) (output) (text "select_n_to_the_cfi_flash_0 " (rect 0 0 134 16)(font "Arial" (font_size 8))) -(text "select_n_to_the_cfi_flash_0 " (rect 367 297 501 313)(font "Arial" (font_size 8))) -(line (pt 512 304)(pt 528 304)(line_width 1)) +(text "select_n_to_the_cfi_flash_0 " (rect 287 297 421 313)(font "Arial" (font_size 8))) +(line (pt 432 304)(pt 448 304)(line_width 1)) ) (port -(pt 528 320) +(pt 448 320) (output) (text "tri_state_bridge_0_address[21..0] " (rect 0 0 163 16)(font "Arial" (font_size 8))) -(text "tri_state_bridge_0_address[21..0] " (rect 337 313 501 329)(font "Arial" (font_size 8))) -(line (pt 512 320)(pt 528 320)(line_width 3)) +(text "tri_state_bridge_0_address[21..0] " (rect 257 313 421 329)(font "Arial" (font_size 8))) +(line (pt 432 320)(pt 448 320)(line_width 3)) ) (port -(pt 528 336) +(pt 448 336) (bidir) (text "tri_state_bridge_0_data[7..0] " (rect 0 0 139 16)(font "Arial" (font_size 8))) -(text "tri_state_bridge_0_data[7..0] " (rect 362 329 501 345)(font "Arial" (font_size 8))) -(line (pt 512 336)(pt 528 336)(line_width 3)) +(text "tri_state_bridge_0_data[7..0] " (rect 282 329 421 345)(font "Arial" (font_size 8))) +(line (pt 432 336)(pt 448 336)(line_width 3)) ) (port -(pt 528 352) +(pt 448 352) (output) (text "tri_state_bridge_0_readn " (rect 0 0 122 16)(font "Arial" (font_size 8))) -(text "tri_state_bridge_0_readn " (rect 379 345 501 361)(font "Arial" (font_size 8))) -(line (pt 512 352)(pt 528 352)(line_width 1)) +(text "tri_state_bridge_0_readn " (rect 299 345 421 361)(font "Arial" (font_size 8))) +(line (pt 432 352)(pt 448 352)(line_width 1)) ) (port -(pt 528 368) +(pt 448 368) (output) (text "write_n_to_the_cfi_flash_0 " (rect 0 0 128 16)(font "Arial" (font_size 8))) -(text "write_n_to_the_cfi_flash_0 " (rect 372 361 501 377)(font "Arial" (font_size 8))) -(line (pt 512 368)(pt 528 368)(line_width 1)) +(text "write_n_to_the_cfi_flash_0 " (rect 292 361 421 377)(font "Arial" (font_size 8))) +(line (pt 432 368)(pt 448 368)(line_width 1)) ) (port -(pt 528 400) +(pt 448 400) (output) -(text "ena_10_from_the_triple_speed_ethernet_0 " (rect 0 0 208 16)(font "Arial" (font_size 8))) -(text "ena_10_from_the_triple_speed_ethernet_0 " (rect 292 393 501 409)(font "Arial" (font_size 8))) -(line (pt 512 400)(pt 528 400)(line_width 1)) +(text "ena_10_from_the_tse_mac " (rect 0 0 132 16)(font "Arial" (font_size 8))) +(text "ena_10_from_the_tse_mac " (rect 288 393 421 409)(font "Arial" (font_size 8))) +(line (pt 432 400)(pt 448 400)(line_width 1)) ) (port -(pt 528 416) +(pt 448 416) (output) -(text "eth_mode_from_the_triple_speed_ethernet_0 " (rect 0 0 220 16)(font "Arial" (font_size 8))) -(text "eth_mode_from_the_triple_speed_ethernet_0 " (rect 281 409 501 425)(font "Arial" (font_size 8))) -(line (pt 512 416)(pt 528 416)(line_width 1)) +(text "eth_mode_from_the_tse_mac " (rect 0 0 144 16)(font "Arial" (font_size 8))) +(text "eth_mode_from_the_tse_mac " (rect 277 409 421 425)(font "Arial" (font_size 8))) +(line (pt 432 416)(pt 448 416)(line_width 1)) ) (port -(pt 528 432) +(pt 448 432) (output) -(text "gm_tx_d_from_the_triple_speed_ethernet_0[7..0] " (rect 0 0 237 16)(font "Arial" (font_size 8))) -(text "gm_tx_d_from_the_triple_speed_ethernet_0[7..0] " (rect 264 425 501 441)(font "Arial" (font_size 8))) -(line (pt 512 432)(pt 528 432)(line_width 3)) +(text "gm_tx_d_from_the_tse_mac[7..0] " (rect 0 0 161 16)(font "Arial" (font_size 8))) +(text "gm_tx_d_from_the_tse_mac[7..0] " (rect 260 425 421 441)(font "Arial" (font_size 8))) +(line (pt 432 432)(pt 448 432)(line_width 3)) ) (port -(pt 528 448) +(pt 448 448) (output) -(text "gm_tx_en_from_the_triple_speed_ethernet_0 " (rect 0 0 219 16)(font "Arial" (font_size 8))) -(text "gm_tx_en_from_the_triple_speed_ethernet_0 " (rect 282 441 501 457)(font "Arial" (font_size 8))) -(line (pt 512 448)(pt 528 448)(line_width 1)) +(text "gm_tx_en_from_the_tse_mac " (rect 0 0 143 16)(font "Arial" (font_size 8))) +(text "gm_tx_en_from_the_tse_mac " (rect 278 441 421 457)(font "Arial" (font_size 8))) +(line (pt 432 448)(pt 448 448)(line_width 1)) ) (port -(pt 528 464) +(pt 448 464) (output) -(text "gm_tx_err_from_the_triple_speed_ethernet_0 " (rect 0 0 220 16)(font "Arial" (font_size 8))) -(text "gm_tx_err_from_the_triple_speed_ethernet_0 " (rect 281 457 501 473)(font "Arial" (font_size 8))) -(line (pt 512 464)(pt 528 464)(line_width 1)) +(text "gm_tx_err_from_the_tse_mac " (rect 0 0 144 16)(font "Arial" (font_size 8))) +(text "gm_tx_err_from_the_tse_mac " (rect 277 457 421 473)(font "Arial" (font_size 8))) +(line (pt 432 464)(pt 448 464)(line_width 1)) ) (port -(pt 528 480) +(pt 448 480) (output) -(text "m_tx_d_from_the_triple_speed_ethernet_0[3..0] " (rect 0 0 230 16)(font "Arial" (font_size 8))) -(text "m_tx_d_from_the_triple_speed_ethernet_0[3..0] " (rect 270 473 501 489)(font "Arial" (font_size 8))) -(line (pt 512 480)(pt 528 480)(line_width 3)) +(text "m_tx_d_from_the_tse_mac[3..0] " (rect 0 0 155 16)(font "Arial" (font_size 8))) +(text "m_tx_d_from_the_tse_mac[3..0] " (rect 266 473 421 489)(font "Arial" (font_size 8))) +(line (pt 432 480)(pt 448 480)(line_width 3)) ) (port -(pt 528 496) +(pt 448 496) (output) -(text "m_tx_en_from_the_triple_speed_ethernet_0 " (rect 0 0 212 16)(font "Arial" (font_size 8))) -(text "m_tx_en_from_the_triple_speed_ethernet_0 " (rect 288 489 501 505)(font "Arial" (font_size 8))) -(line (pt 512 496)(pt 528 496)(line_width 1)) +(text "m_tx_en_from_the_tse_mac " (rect 0 0 137 16)(font "Arial" (font_size 8))) +(text "m_tx_en_from_the_tse_mac " (rect 284 489 421 505)(font "Arial" (font_size 8))) +(line (pt 432 496)(pt 448 496)(line_width 1)) ) (port -(pt 528 512) +(pt 448 512) (output) -(text "m_tx_err_from_the_triple_speed_ethernet_0 " (rect 0 0 214 16)(font "Arial" (font_size 8))) -(text "m_tx_err_from_the_triple_speed_ethernet_0 " (rect 287 505 501 521)(font "Arial" (font_size 8))) -(line (pt 512 512)(pt 528 512)(line_width 1)) +(text "m_tx_err_from_the_tse_mac " (rect 0 0 138 16)(font "Arial" (font_size 8))) +(text "m_tx_err_from_the_tse_mac " (rect 283 505 421 521)(font "Arial" (font_size 8))) +(line (pt 432 512)(pt 448 512)(line_width 1)) ) (port -(pt 528 528) +(pt 448 528) (output) -(text "mdc_from_the_triple_speed_ethernet_0 " (rect 0 0 192 16)(font "Arial" (font_size 8))) -(text "mdc_from_the_triple_speed_ethernet_0 " (rect 308 521 501 537)(font "Arial" (font_size 8))) -(line (pt 512 528)(pt 528 528)(line_width 1)) +(text "mdc_from_the_tse_mac " (rect 0 0 117 16)(font "Arial" (font_size 8))) +(text "mdc_from_the_tse_mac " (rect 304 521 421 537)(font "Arial" (font_size 8))) +(line (pt 432 528)(pt 448 528)(line_width 1)) ) (port -(pt 528 544) +(pt 448 544) (output) -(text "mdio_oen_from_the_triple_speed_ethernet_0 " (rect 0 0 220 16)(font "Arial" (font_size 8))) -(text "mdio_oen_from_the_triple_speed_ethernet_0 " (rect 281 537 501 553)(font "Arial" (font_size 8))) -(line (pt 512 544)(pt 528 544)(line_width 1)) +(text "mdio_oen_from_the_tse_mac " (rect 0 0 144 16)(font "Arial" (font_size 8))) +(text "mdio_oen_from_the_tse_mac " (rect 277 537 421 553)(font "Arial" (font_size 8))) +(line (pt 432 544)(pt 448 544)(line_width 1)) ) (port -(pt 528 560) +(pt 448 560) (output) -(text "mdio_out_from_the_triple_speed_ethernet_0 " (rect 0 0 217 16)(font "Arial" (font_size 8))) -(text "mdio_out_from_the_triple_speed_ethernet_0 " (rect 284 553 501 569)(font "Arial" (font_size 8))) -(line (pt 512 560)(pt 528 560)(line_width 1)) +(text "mdio_out_from_the_tse_mac " (rect 0 0 141 16)(font "Arial" (font_size 8))) +(text "mdio_out_from_the_tse_mac " (rect 280 553 421 569)(font "Arial" (font_size 8))) +(line (pt 432 560)(pt 448 560)(line_width 1)) ) (port -(pt 528 624) +(pt 448 624) (output) (text "txd_from_the_uart_0 " (rect 0 0 98 16)(font "Arial" (font_size 8))) -(text "txd_from_the_uart_0 " (rect 402 617 501 633)(font "Arial" (font_size 8))) -(line (pt 512 624)(pt 528 624)(line_width 1)) +(text "txd_from_the_uart_0 " (rect 322 617 421 633)(font "Arial" (font_size 8))) +(line (pt 432 624)(pt 448 624)(line_width 1)) ) (drawing -(line (pt 16 64)(pt 511 64)(color 0 0 0)(dotted)(line_width 1)) -(line (pt 16 128)(pt 511 128)(color 0 0 0)(dotted)(line_width 1)) -(line (pt 16 288)(pt 511 288)(color 0 0 0)(dotted)(line_width 1)) -(line (pt 16 384)(pt 511 384)(color 0 0 0)(dotted)(line_width 1)) -(line (pt 16 608)(pt 511 608)(color 0 0 0)(dotted)(line_width 1)) -(rectangle (rect 16 16 512 640)(line_width 1))) +(line (pt 16 64)(pt 431 64)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 128)(pt 431 128)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 288)(pt 431 288)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 384)(pt 431 384)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 608)(pt 431 608)(color 0 0 0)(dotted)(line_width 1)) +(rectangle (rect 16 16 432 640)(line_width 1))) ) diff --git a/quartus/dionysos_nios2mmu.qsf b/quartus/dionysos_nios2mmu.qsf index de2936f..f9bb63c 100644 --- a/quartus/dionysos_nios2mmu.qsf +++ b/quartus/dionysos_nios2mmu.qsf @@ -187,8 +187,8 @@ set_location_assignment PIN_AB9 -to et_phy1_int_2_i set_location_assignment PIN_U11 -to et_phy1_mdc_o set_location_assignment PIN_V11 -to et_phy1_mdio_io set_location_assignment PIN_W10 -to rst_et_phy1_n_o -#set_location_assignment PIN_Y10 -to gen_led_r_o[3] -#set_location_assignment PIN_AA10 -to gen_led_g_o[3] +set_location_assignment PIN_Y10 -to gen_led_r_o[3] +set_location_assignment PIN_AA10 -to gen_led_g_o[3] # FPGA bank 4 # ----------- @@ -221,15 +221,15 @@ set_location_assignment PIN_W10 -to rst_et_phy1_n_o #set_location_assignment PIN_AB17 -to otg_dack0_n_o #set_location_assignment PIN_AA18 -to otg_dack1_n_o set_location_assignment PIN_AB19 -to et_phy2_rx_dv_1_i -#set_location_assignment PIN_W17 -to gen_led_r_o[6] +set_location_assignment PIN_W17 -to gen_led_r_o[6] set_location_assignment PIN_Y17 -to et_phy2_tx_en_1_o -#set_location_assignment PIN_AB20 -to gen_led_r_o[2] -#set_location_assignment PIN_V16 -to gen_led_g_o[2] +set_location_assignment PIN_AB20 -to gen_led_r_o[2] +set_location_assignment PIN_V16 -to gen_led_g_o[2] #set_location_assignment PIN_U16 -to reserve4_i #set_location_assignment PIN_U17 -to reserve5_i set_location_assignment PIN_T16 -to aux_clk_p_o set_location_assignment PIN_R16 -to aux_clk_n_o -#set_location_assignment PIN_R15 -to gen_led_g_o[6] +set_location_assignment PIN_R15 -to gen_led_g_o[6] # FPGA bank 5 # ----------- @@ -374,8 +374,8 @@ set_location_assignment PIN_F11 -to dram_a_o[12] #set_location_assignment PIN_H11 -to sdfe_aux_3_4_i #set_location_assignment PIN_H10 -to sdfe_aux_3_5_i #set_location_assignment PIN_A5 -to sdfe_refclk_3_i -#set_location_assignment PIN_B5 -to gen_led_r_o[1] -#set_location_assignment PIN_G10 -to gen_led_g_o[1] +set_location_assignment PIN_B5 -to gen_led_r_o[1] +set_location_assignment PIN_G10 -to gen_led_g_o[1] #set_location_assignment PIN_F10 -to sdfe_scdi_o #set_location_assignment PIN_C6 -to sdfe_scdo_i #set_location_assignment PIN_D7 -to sdfe_scck_o @@ -421,6 +421,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_reset_n_i set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reserve8_i set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_r_o[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_g_o[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to et_phy_clk_50mhz_o set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top @@ -447,4 +448,5 @@ set_global_assignment -name QIP_FILE dionysos_nios2mmu.qip set_global_assignment -name VHDL_FILE dionysos_nios2mmu.vhd set_global_assignment -name SDC_FILE dionysos_nios2mmu.sdc + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/quartus/dionysos_nios2mmu.sopc b/quartus/dionysos_nios2mmu.sopc index 1fc4c41..3ceafcf 100644 --- a/quartus/dionysos_nios2mmu.sopc +++ b/quartus/dionysos_nios2mmu.sopc @@ -4,6 +4,11 @@ { element jtag_uart_0.avalon_jtag_slave { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { value = "41953472"; @@ -14,7 +19,7 @@ { datum _sortIndex { - value = "5"; + value = "6"; type = "int"; } datum megawizard_uipreferences @@ -31,14 +36,32 @@ type = "int"; } } - element triple_speed_ethernet_0.control_port + element tse_mac.control_port { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { value = "41952256"; type = "long"; } } + element sysid.control_slave + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "4759552"; + type = "long"; + } + } element cpu_0 { datum _sortIndex @@ -48,23 +71,33 @@ } datum megawizard_uipreferences { - value = "{}"; + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } } - element sgdma_tx.csr + element sgdma_rx.csr { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { - value = "41953344"; + value = "41953280"; type = "long"; } } - element sgdma_rx.csr + element sgdma_tx.csr { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { - value = "41953280"; + value = "41953344"; type = "long"; } } @@ -72,7 +105,7 @@ { datum _sortIndex { - value = "13"; + value = "14"; type = "int"; } datum megawizard_uipreferences @@ -86,6 +119,11 @@ } element epcs_flash_controller_0.epcs_control_port { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { value = "41949184"; @@ -96,7 +134,7 @@ { datum _sortIndex { - value = "7"; + value = "8"; type = "int"; } datum megawizard_uipreferences @@ -107,6 +145,11 @@ } element cpu_0.jtag_debug_module { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { value = "41947136"; @@ -117,7 +160,7 @@ { datum _sortIndex { - value = "9"; + value = "10"; type = "int"; } datum megawizard_uipreferences @@ -130,7 +173,7 @@ { datum _sortIndex { - value = "2"; + value = "3"; type = "int"; } datum megawizard_uipreferences @@ -139,61 +182,104 @@ type = "String"; } } - element cfi_flash_0.s1 + element onchip_memory2_0.s1 { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { - value = "37748736"; + value = "41951232"; type = "long"; } } - element uart_0.s1 + element descriptor_memory.s1 { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { - value = "41953440"; + value = "75759616"; type = "long"; } } - element descriptor_memory.s1 + element sdram_0.s1 { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { - value = "0"; + value = "16777216"; type = "long"; } } - element onchip_memory2_0.s1 + element timer_0.s1 { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { - value = "41951232"; + value = "41953408"; type = "long"; } } - element timer_0.s1 + element watchdog_timer.s1 { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { - value = "41953408"; + value = "76021760"; type = "long"; } } - element sdram_0.s1 + element cfi_flash_0.s1 { datum _lockedAddress { - value = "0"; + value = "1"; type = "boolean"; } datum baseAddress { - value = "16777216"; + value = "37748736"; + type = "long"; + } + } + element uart_0.s1 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "41953440"; type = "long"; } } element onchip_memory2_0.s2 { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { value = "41951232"; @@ -204,7 +290,7 @@ { datum _sortIndex { - value = "3"; + value = "4"; type = "int"; } datum megawizard_uipreferences @@ -217,12 +303,12 @@ { datum _sortIndex { - value = "11"; + value = "12"; type = "int"; } datum megawizard_uipreferences { - value = "{}"; + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } } @@ -230,7 +316,20 @@ { datum _sortIndex { - value = "12"; + value = "13"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; + type = "String"; + } + } + element sysid + { + datum _sortIndex + { + value = "2"; type = "int"; } datum megawizard_uipreferences @@ -243,12 +342,12 @@ { datum _sortIndex { - value = "6"; + value = "7"; type = "int"; } datum megawizard_uipreferences { - value = "{}"; + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } } @@ -256,7 +355,7 @@ { datum _sortIndex { - value = "4"; + value = "5"; type = "int"; } datum megawizard_uipreferences @@ -265,16 +364,16 @@ type = "String"; } } - element triple_speed_ethernet_0 + element tse_mac { datum _sortIndex { - value = "10"; + value = "11"; type = "int"; } datum megawizard_uipreferences { - value = "{}"; + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } } @@ -282,7 +381,20 @@ { datum _sortIndex { - value = "8"; + value = "9"; + type = "int"; + } + datum megawizard_uipreferences + { + value = "{}"; + type = "String"; + } + } + element watchdog_timer + { + datum _sortIndex + { + value = "15"; type = "int"; } datum megawizard_uipreferences @@ -298,8 +410,8 @@ dionysos_nios2mmu.qpf - - + + @@ -336,7 +448,7 @@ - + @@ -501,11 +613,7 @@ - + @@ -622,6 +730,22 @@ + + + + + + + + + + + + + end="tse_mac.receive_clock_connection" /> + end="tse_mac.transmit_clock_connection" /> + end="tse_mac.control_port"> @@ -798,7 +922,7 @@ kind="clock" version="9.1" start="clk_0.clk" - end="triple_speed_ethernet_0.control_port_clock_connection" /> + end="tse_mac.control_port_clock_connection" /> - + - + @@ -859,13 +983,13 @@ + end="tse_mac.transmit" /> @@ -876,7 +1000,7 @@ start="sgdma_tx.descriptor_read" end="descriptor_memory.s1"> - + - + - + + + + + + + + + + + + + + diff --git a/quartus/dionysos_nios2mmu.sopcinfo b/quartus/dionysos_nios2mmu.sopcinfo index 5464541..24c252a 100644 --- a/quartus/dionysos_nios2mmu.sopcinfo +++ b/quartus/dionysos_nios2mmu.sopcinfo @@ -4,7 +4,7 @@ kind="com_altera_sopcmodel_ensemble_Ensemble" version="9.1"> - + com.altera.entityinterfaces.moduleext.IDeviceFamily$EDeviceFamily @@ -48,7 +48,7 @@ long - -62283505486 + -77315762035 false true true @@ -56,7 +56,7 @@ long - 1280742475274 + 1295440989718 false true true @@ -241,21 +241,21 @@ parameters are a RESULT of the module parameters. --> false - triple_speed_ethernet_0 + tse_mac receive_clock_connection - triple_speed_ethernet_0.receive_clock_connection + tse_mac.receive_clock_connection false - triple_speed_ethernet_0 + tse_mac transmit_clock_connection - triple_speed_ethernet_0.transmit_clock_connection + tse_mac.transmit_clock_connection false - triple_speed_ethernet_0 + tse_mac control_port_clock_connection - triple_speed_ethernet_0.control_port_clock_connection + tse_mac.control_port_clock_connection false @@ -275,6 +275,18 @@ parameters are a RESULT of the module parameters. --> clk sgdma_tx.clk + + false + watchdog_timer + clk + watchdog_timer.clk + + + false + sysid + clk + sysid.clk + embeddedsw.configuration.resetSlave - cfi_flash_0.s1 + sdram_0.s1 embeddedsw.configuration.resetOffset @@ -485,7 +497,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.RESET_ADDR - 0xc2400000 + 0xc1000000 embeddedsw.CMacro.BREAK_ADDR @@ -537,7 +549,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.DATA_ADDR_WIDTH - 26 + 27 embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS @@ -793,7 +805,7 @@ the requested settings for a module instance. --> com.altera.entityinterfaces.IConnectionPoint - cfi_flash_0.s1 + sdram_0.s1 false true true @@ -2110,7 +2122,7 @@ parameters are a RESULT of the module parameters. --> d_address Output - 26 + 27 address @@ -2219,9 +2231,9 @@ parameters are a RESULT of the module parameters. --> false - triple_speed_ethernet_0 + tse_mac control_port - triple_speed_ethernet_0.control_port + tse_mac.control_port 41952256 1024 @@ -2246,9 +2258,25 @@ parameters are a RESULT of the module parameters. --> descriptor_memory s1 descriptor_memory.s1 - 0 + 75759616 8192 + + false + watchdog_timer + s1 + watchdog_timer.s1 + 76021760 + 32 + + + false + sysid + control_slave + sysid.control_slave + 4759552 + 8 + sgdma_tx.csr_irq 5 + + false + watchdog_timer + irq + watchdog_timer.irq + 6 + dcm0_address Output - 26 + 27 address @@ -8665,10 +8700,7 @@ parameters are a RESULT of the module parameters. --> - + @@ -11223,7 +11255,7 @@ parameters are a RESULT of the module parameters. --> descriptor_memory s1 descriptor_memory.s1 - 0 + 75759616 8192 @@ -11510,7 +11542,7 @@ parameters are a RESULT of the module parameters. --> descriptor_memory s1 descriptor_memory.s1 - 0 + 75759616 8192 @@ -13551,7 +13583,7 @@ parameters are a RESULT of the module parameters. --> descriptor_memory s1 descriptor_memory.s1 - 0 + 75759616 8192 @@ -13838,7 +13870,7 @@ parameters are a RESULT of the module parameters. --> descriptor_memory s1 descriptor_memory.s1 - 0 + 75759616 8192 @@ -14318,206 +14350,132 @@ parameters are a RESULT of the module parameters. --> - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - cpu_0 - clk - - - - int + + + + embeddedsw.CMacro.ALWAYS_RUN 1 - false - true - true - true - - - long - 0x02801000 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - + + + embeddedsw.CMacro.FIXED_PERIOD + 1 + + + embeddedsw.CMacro.SNAPSHOT + 0 + + + embeddedsw.CMacro.PERIOD + 10 + + + embeddedsw.CMacro.PERIOD_UNITS + "s" + + + embeddedsw.CMacro.RESET_OUTPUT + 1 + + + embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT + 0 + + + embeddedsw.CMacro.FREQ + 50000000u + + + embeddedsw.CMacro.LOAD_VALUE + 499999999ULL + + + embeddedsw.CMacro.COUNTER_SIZE + 32 + + + embeddedsw.CMacro.MULT + 1.0 + + + embeddedsw.CMacro.TICKS_PER_SEC + 1u + + boolean - false + true false - true + false true true - cpu_0 - instruction_master - cpu_0 - jtag_debug_module - - - + int - 1 + 32 false true true true - - long - 0x02801000 + + boolean + true false - true + false true true - + java.lang.String - UNKNOWN + 10 false true true true - - boolean - false + + com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.AlteraAvalonTimer$TimerPeriodUnit + SEC false true true true - cpu_0 - data_master - cpu_0 - jtag_debug_module - - - - java.lang.String - UNKNOWN + + boolean + true false - true + false true true - + boolean false false - true - true - true - - clk_0 - clk - sdram_0 - clk - - - - int - 1 - false - true + false true true - + long - 0x01000000 - false - true - true - true - - - java.lang.String - UNKNOWN + 50000000 false true true true - + boolean false false - true - true - true - - cpu_0 - instruction_master - sdram_0 - s1 - - - - int - 1 - false - true + false true true - - long - 0x01000000 + + com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.TimerPresets + WATCHDOG false true true @@ -14539,13 +14497,1140 @@ parameters are a RESULT of the module parameters. --> true true - cpu_0 - data_master - sdram_0 - s1 - - + + + java.lang.Long + 50000000 + true + true + false + true + + + java.lang.Boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isTimerDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + writedata + Input + 16 + writedata + + + readdata + Output + 16 + readdata + + + chipselect + Input + 1 + chipselect + + + write_n + Input + 1 + write_n + + + resetrequest + Output + 1 + resetrequest + + + + + + com.altera.entityinterfaces.IConnectionPoint + watchdog_timer.s1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.ID + 6350743u + + + embeddedsw.CMacro.TIMESTAMP + 1295440990u + + + long + 6350743 + true + true + true + true + + + long + 1295440990 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clock + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 2 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 1 + address + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + cpu_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02801000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + instruction_master + cpu_0 + jtag_debug_module + + + + int + 1 + false + true + true + true + + + long + 0x02801000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + cpu_0 + jtag_debug_module + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + sdram_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x01000000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + instruction_master + sdram_0 + s1 + + + + int + 1 + false + true + true + true + + + long + 0x01000000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + sdram_0 + s1 + + s2 + end="tse_mac.receive_clock_connection"> java.lang.String UNKNOWN @@ -15354,15 +16439,15 @@ parameters are a RESULT of the module parameters. --> clk_0 clk - triple_speed_ethernet_0 + tse_mac receive_clock_connection + end="tse_mac.transmit_clock_connection"> java.lang.String UNKNOWN @@ -15381,15 +16466,15 @@ parameters are a RESULT of the module parameters. --> clk_0 clk - triple_speed_ethernet_0 + tse_mac transmit_clock_connection + end="tse_mac.control_port"> int 1 @@ -15424,15 +16509,15 @@ parameters are a RESULT of the module parameters. --> cpu_0 data_master - triple_speed_ethernet_0 + tse_mac control_port + end="tse_mac.control_port_clock_connection"> java.lang.String UNKNOWN @@ -15451,7 +16536,7 @@ parameters are a RESULT of the module parameters. --> clk_0 clk - triple_speed_ethernet_0 + tse_mac control_port_clock_connection long - 0x0000 + 0x04840000 false true true @@ -15750,7 +16835,7 @@ parameters are a RESULT of the module parameters. --> long - 0x0000 + 0x04840000 false true true @@ -15821,10 +16906,10 @@ parameters are a RESULT of the module parameters. --> s1 java.lang.String @@ -15842,17 +16927,216 @@ parameters are a RESULT of the module parameters. --> true true - triple_speed_ethernet_0 - receive - sgdma_rx - in + tse_mac + receive + sgdma_rx + in + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sgdma_tx + out + tse_mac + transmit + + + + int + 1 + false + true + true + true + + + long + 0x01000000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sgdma_tx + m_read + sdram_0 + s1 + + + + int + 1 + false + true + true + true + + + long + 0x04840000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sgdma_tx + descriptor_read + descriptor_memory + s1 + + + + int + 1 + false + true + true + true + + + long + 0x04840000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sgdma_tx + descriptor_write + descriptor_memory + s1 + + + + int + 1 + false + true + true + true + + + long + 0x04840000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + descriptor_memory + s1 + start="clk_0.clk" + end="watchdog_timer.clk"> java.lang.String UNKNOWN @@ -15869,17 +17153,17 @@ parameters are a RESULT of the module parameters. --> true true - sgdma_tx - out - triple_speed_ethernet_0 - transmit + clk_0 + clk + watchdog_timer + clk + start="cpu_0.data_master" + end="watchdog_timer.s1"> int 1 @@ -15890,7 +17174,7 @@ parameters are a RESULT of the module parameters. --> long - 0x01000000 + 0x04880000 false true true @@ -15912,28 +17196,20 @@ parameters are a RESULT of the module parameters. --> true true - sgdma_tx - m_read - sdram_0 + cpu_0 + data_master + watchdog_timer s1 - + name="cpu_0.d_irq/watchdog_timer.irq" + kind="interrupt" + version="9.1" + start="cpu_0.d_irq" + end="watchdog_timer.irq"> + int - 1 - false - true - true - true - - - long - 0x0000 + 6 false true true @@ -15955,33 +17231,17 @@ parameters are a RESULT of the module parameters. --> true true - sgdma_tx - descriptor_read - descriptor_memory - s1 + cpu_0 + d_irq + watchdog_timer + irq - - int - 1 - false - true - true - true - - - long - 0x0000 - false - true - true - true - + name="clk_0.clk/sysid.clk" + kind="clock" + version="9.1" + start="clk_0.clk" + end="sysid.clk"> java.lang.String UNKNOWN @@ -15998,17 +17258,17 @@ parameters are a RESULT of the module parameters. --> true true - sgdma_tx - descriptor_write - descriptor_memory - s1 + clk_0 + clk + sysid + clk + end="sysid.control_slave"> int 1 @@ -16019,7 +17279,7 @@ parameters are a RESULT of the module parameters. --> long - 0x0000 + 0x0048a000 false true true @@ -16043,19 +17303,11 @@ parameters are a RESULT of the module parameters. --> cpu_0 data_master - descriptor_memory - s1 + sysid + control_slave - 1 - interrupt_receiver - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Receiver - 9.1 - - - 6 + 7 interrupt com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -16064,74 +17316,82 @@ parameters are a RESULT of the module parameters. --> 1 - altera_nios2 + altera_avalon_tri_state_bridge com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Nios II Processor + Avalon-MM Tristate Bridge 9.1 - 10 - avalon_master + 4 + conduit com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Master - 9.1 + Conduit Endpoint + 7.1 - 2 - avalon_streaming_sink + 1 + interrupt_receiver com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Streaming Sink + Interrupt Receiver 9.1 1 - altera_avalon_jtag_uart + altera_avalon_new_sdram_controller com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - JTAG UART + SDRAM Controller 9.1 1 - altera_avalon_timer + avalon_tristate_slave com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Interval Timer + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Tristate Slave 9.1 1 - triple_speed_ethernet + altera_avalon_jtag_uart com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Triple-Speed Ethernet + JTAG UART 9.1 1 - avalon_tristate + altera_nios2 com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Tristate Connection + com.altera.entityinterfaces.IModule + Nios II Processor 9.1 - 1 - nios_custom_instruction_master + 7 + interrupt_sender com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Custom Instruction Master + Interrupt Sender 9.1 + + 25 + avalon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection + 6.1 + 1 - altera_avalon_uart + avalon_tristate_master com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - UART (RS-232 Serial Port) + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Tristate Master 9.1 @@ -16142,52 +17402,36 @@ parameters are a RESULT of the module parameters. --> Avalon Streaming Connection 9.1 - - 4 - conduit - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit Endpoint - 7.1 - 2 - avalon_streaming_source + altera_avalon_onchip_memory2 com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Streaming Source + com.altera.entityinterfaces.IModule + On-Chip Memory (RAM or ROM) 9.1 1 - clock_source + triple_speed_ethernet com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Clock Source - 9.1 - - - 6 - interrupt_sender - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Sender + Triple-Speed Ethernet 9.1 1 - avalon_tristate_master + avalon_tristate com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Tristate Master + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Tristate Connection 9.1 1 - avalon_tristate_slave + nios_custom_instruction_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Tristate Slave + Custom Instruction Master 9.1 @@ -16199,11 +17443,19 @@ parameters are a RESULT of the module parameters. --> 9.1 - 1 - altera_avalon_tri_state_bridge + 10 + avalon_master com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Avalon-MM Tristate Bridge + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Master + 9.1 + + + 2 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source 9.1 @@ -16215,7 +17467,7 @@ parameters are a RESULT of the module parameters. --> 9.1 - 16 + 18 clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -16223,27 +17475,19 @@ parameters are a RESULT of the module parameters. --> 9.1 - 23 - avalon - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Connection - 6.1 - - - 13 - avalon_slave + 19 + clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Slave + Clock Input 9.1 - 2 - altera_avalon_onchip_memory2 + 1 + clock_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - On-Chip Memory (RAM or ROM) + Clock Source 9.1 @@ -16255,11 +17499,11 @@ parameters are a RESULT of the module parameters. --> 9.1 - 1 - altera_avalon_new_sdram_controller + 15 + avalon_slave com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - SDRAM Controller + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave 9.1 @@ -16271,13 +17515,37 @@ parameters are a RESULT of the module parameters. --> 9.1 - 17 - clock_sink + 1 + altera_avalon_sysid + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + System ID Peripheral + 9.1 + + + 1 + altera_avalon_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + UART (RS-232 Serial Port) + 9.1 + + + 2 + altera_avalon_timer + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Interval Timer + 9.1 + + + 2 + avalon_streaming_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input + Avalon Streaming Sink 9.1 9.1sp2 350 - 0023AE674DE00000012A3232FDE1 + 0023AE674DE00000012D9E4A9A2B -- cgit v1.2.3-54-g00ecf