From 82dcb83ed8cd6bfe5d79541a972028b650dc03c3 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 26 Mar 2010 15:25:16 +0100 Subject: Initial commit --- .gitignore | 1 + dionysos_top.vhd | 235 + lib/altera/cyc3_pll_0ns.qip | 5 + lib/altera/cyc3_pll_0ns.vhd | 351 ++ lib/altera/cyc3_pll_m3ns.qip | 5 + lib/altera/cyc3_pll_m3ns.vhd | 351 ++ lib/altera/cyc3pll_eth_phy.qip | 5 + lib/altera/sinet_pll.qip | 5 + lib/altera/sinet_pll.vhd | 444 ++ lib/misc/components/reset_sync.vhd | 88 + quartus/dionysos_nios2mmu.bsf | 166 + quartus/dionysos_nios2mmu.qpf | 30 + quartus/dionysos_nios2mmu.qsf | 438 ++ quartus/dionysos_nios2mmu.sdc | 202 + quartus/dionysos_nios2mmu.sopc | 566 +++ quartus/dionysos_nios2mmu.sopcinfo | 9792 ++++++++++++++++++++++++++++++++++++ quartus/dionysos_sinet.qsf | 639 +++ 17 files changed, 13323 insertions(+) create mode 100644 .gitignore create mode 100644 dionysos_top.vhd create mode 100644 lib/altera/cyc3_pll_0ns.qip create mode 100644 lib/altera/cyc3_pll_0ns.vhd create mode 100644 lib/altera/cyc3_pll_m3ns.qip create mode 100644 lib/altera/cyc3_pll_m3ns.vhd create mode 100644 lib/altera/cyc3pll_eth_phy.qip create mode 100644 lib/altera/sinet_pll.qip create mode 100644 lib/altera/sinet_pll.vhd create mode 100644 lib/misc/components/reset_sync.vhd create mode 100644 quartus/dionysos_nios2mmu.bsf create mode 100644 quartus/dionysos_nios2mmu.qpf create mode 100644 quartus/dionysos_nios2mmu.qsf create mode 100644 quartus/dionysos_nios2mmu.sdc create mode 100644 quartus/dionysos_nios2mmu.sopc create mode 100644 quartus/dionysos_nios2mmu.sopcinfo create mode 100644 quartus/dionysos_sinet.qsf diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..f0fb01b --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +quartus/.sopc_builder diff --git a/dionysos_top.vhd b/dionysos_top.vhd new file mode 100644 index 0000000..faa6b65 --- /dev/null +++ b/dionysos_top.vhd @@ -0,0 +1,235 @@ +------------------------------------------------------------------ +-- _____ ______ _____ - +-- |_ _| | ____|/ ____| Institute of Embedded Systems - +-- | | _ __ | |__ | (___ Zuercher Hochschule fuer - +-- | | | '_ \| __| \___ \ angewandte Wissenschaften - +-- _| |_| | | | |____ ____) | (University of Applied Sciences) - +-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +------------------------------------------------------------------ +-- $LastChangedDate: 2008-02-06 14:28:53 +0100 (Mi, 06 Feb 2008) $ +-- $Rev: 828 $ +-- $Author: ffar $ +----------------------------------------------------------------- +-- +-- Change History +-- Date |Name |Modification +------------|----------|----------------------------------------- +-- 14.02.07 | kelt |file created for SInet +------------|----------|----------------------------------------- +-- 22.02.10 | klto |file adjusted for dionysos-nios2mmu project +----------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library ines_misc; + use ines_misc.reset_sync_pkg.all; + +--! \brief Top file for design on Dionysos board +entity dionysos_top is + port( + --!@name Clock and reset inputs + --@{ + clock_50_i : in std_logic; --! 50 MHz system clock + fpga_reset_n_i : in std_logic; --! FPGA reset from voltage monitor + --@} + + --!@name Cyclone EPCS config device interface + --@{ + --! \anchor epcs_grp + config_ce_n_o : out std_logic; --! Cyclone EPCS config device chip select + config_asd0_o : out std_logic; --! Cyclone EPCS config device address + config_data0_i : in std_logic; --! Cyclone EPCS config device data + config_dclk_o : out std_logic; --! Cyclone EPCS config device clock + --@} + + --!@name RS232 for Linux console + --@{ + --! \anchor rs_linux_grp + nios_uart_rxd_i : in std_logic; --! Linux console UART Receiver + nios_uart_txd_o : out std_logic; --! Linux console UART Transmitter + --@} + + --!@name GP-LEDs + --@{ + --! \anchor led_grp + gp_led_o : out std_logic_vector(3 downto 0); --! general purpose LEDs + gen_led_g_o : out std_logic_vector(6 downto 0); --! green LEDs at front cover + gen_led_r_o : out std_logic_vector(6 downto 0); --! red LEDs at front cover + --@} + + --!@name DPDT Switch + --@{ + --! \anchor switch_grp + switch_i : in std_logic_vector(3 downto 0); --! Dip-Switch[3:0] + --@} + + --!@name Reserve Pins + --@{ + reserve0_i : in std_logic; --! unused pin + reserve1_i : in std_logic; --! unused pin + reserve2_i : in std_logic; --! unused pin + reserve3_i : in std_logic; --! unused pin + reserve4_i : in std_logic; --! unused pin + reserve5_i : in std_logic; --! unused pin + reserve6_i : in std_logic; --! unused pin + reserve7_i : in std_logic; --! unused pin + reserve8_i : in std_logic; --! unused pin + --@} + + --!@name SDRAM Interface + --@{ + --! \anchor sdram_grp + dram_d_io : inout std_logic_vector(15 downto 0); --! SDRAM Data bus 16 Bits + dram_a_o : out std_logic_vector(12 downto 0); --! SDRAM Address bus 12 Bits + dram_clk_o : out std_logic; --! SDRAM Clock + dram_cke_o : out std_logic; --! SDRAM Clock Enable + dram_ldqm_o : out std_logic; --! SDRAM Low-byte Data Mask + dram_udqm_o : out std_logic; --! SDRAM High-byte Data Mask + dram_we_n_o : out std_logic; --! SDRAM Write Enable + dram_cas_n_o : out std_logic; --! SDRAM Column Address Strobe + dram_ras_n_o : out std_logic; --! SDRAM Row Address Strobe + dram_cs_n_o : out std_logic; --! SDRAM Chip Select + dram_ba0_n_o : out std_logic; --! SDRAM Bank Address 0 + dram_ba1_n_o : out std_logic; --! SDRAM Bank Address 0 + --@} + + --!@name Flash Interface + --@{ + --! \anchor flash_grp + flash_d_io : inout std_logic_vector(7 downto 0); --! FLASH Data bus 8 Bits + flash_a_o : out std_logic_vector(21 downto 0); --! FLASH Address bus 22 Bits + flash_we_n_o : out std_logic; --! FLASH Write Enable + flash_reset_n_o : out std_logic; --! FLASH Reset + flash_oe_n_o : out std_logic; --! FLASH Output Enable + flash_ce_n_o : out std_logic; --! FLASH Chip Enable + fash_acc_o : out std_logic --! + --@} + ); +end dionysos_top; + +architecture rtl of dionysos_top is + + --! FPGA main clock frequency (50MHz) + constant C_FPGA_FREQ : integer := 50000000; + + --! 50 MHz Clock which is Source Synchronous to the DRAM Data + signal pll_clk_50 : std_logic; + --! 25 MHz Clock + signal pll_clk_25 : std_logic; + --! 12.5 MHz Clock + signal pll_clk_12_5 : std_logic; + --! main design reset after reset circuit + signal reset_n : std_logic; + --! synchronous reset + signal fpga_reset_n_ff : std_logic; + --! Reset for the NIOS. Active in Ethernet Modus (no DSL) + signal reset_nios_n : std_logic; + + --! front pannel LEDs + signal leds : std_logic_vector(15 downto 0); + + --! @name SDRAM Data + --@{ + --! Nios SDRAM controller data mask (byte select) + signal dram_dqm : std_logic_vector(1 downto 0); + --! Nios SDRAM controller bank address + signal dram_ba : std_logic_vector(1 downto 0); + --@} + + --! synchronised on clock dip switch states + signal sw_sync : std_logic_vector(switch_i'range); + + begin +--! @name Components +--@{ + + -- generate ETH-PHY 50MHz clock + + --! PLL to generate all clocks dram clock (shift -3ns) + sinet_pll : entity work.sinet_pll + port map ( + inclk0 => clock_50_i, -- 50 MHz in + c0 => pll_clk_50, -- 50MHz source synchronous clock out + c1 => pll_clk_25, -- 25MHz clock output + c2 => pll_clk_12_5, -- 12.5MHz clock output + c3 => dram_clk_o -- 50MHz clock output (-3ns) + ); + + --! synchronize reset + reset_n_sync : reset_sync + generic map( + STAGES => 2 + ) + port map( + clk_i => pll_clk_50, + reset1_n_i => fpga_reset_n_i, + reset2_n_i => '1', + reset_n_o => fpga_reset_n_ff + ); + + --! Delay reset => Latch in Time from Power up for the RMII-Phy (min 167ms) + reset_gen : reset_sync + generic map( + STAGES => 10000000 --200ms + ) + port map( + clk_i => pll_clk_50, + reset1_n_i => fpga_reset_n_ff, + reset2_n_i => '1', + reset_n_o => reset_n -- reset for all other components + ); + + -- NIOSII CPU + flash_reset_n_o <= '1'; + fash_acc_o <= '0'; -- Hardware Write Protect input (accelerated program operations) + dram_ldqm_o <= dram_dqm(0); + dram_udqm_o <= dram_dqm(1); + dram_ba0_n_o <= dram_ba(0); + dram_ba1_n_o <= dram_ba(1); + reset_nios_n <= reset_n; + + --! \brief Altera SOPC-Builder component + --! \details + --! \li NiosII CPU + --! \li SDRAM Interface + --! \li Flash Interface + --! \li Uart + --! \li EPCS Controller + --! \n See \subpage nios_config_page for details + + cpu : entity work.cpu_0 + port map( + clk => pll_clk_50, + reset_n => reset_nios_n, + + -- the_sdram_0 + zs_addr_from_the_sdram_0 => dram_a_o(11 downto 0), -- dram_a_o(12) is for 32Mbit SDRAM + zs_ba_from_the_sdram_0 => dram_ba, + zs_cas_n_from_the_sdram_0 => dram_cas_n_o, + zs_cke_from_the_sdram_0 => dram_cke_o, + zs_cs_n_from_the_sdram_0 => dram_cs_n_o, + zs_dq_to_and_from_the_sdram_0 => dram_d_io, + zs_dqm_from_the_sdram_0 => dram_dqm, + zs_ras_n_from_the_sdram_0 => dram_ras_n_o, + zs_we_n_from_the_sdram_0 => dram_we_n_o, + + -- the_tri_state_bridge_0_avalon_slave + select_n_to_the_cfi_flash_0 => flash_ce_n_o, + tri_state_bridge_0_address => flash_a_o, + tri_state_bridge_0_data => flash_d_io, + tri_state_bridge_0_readn => flash_oe_n_o, + write_n_to_the_cfi_flash_0 => flash_we_n_o, + + -- the_uart_0 + rxd_to_the_uart_0 => nios_uart_rxd_i, + txd_from_the_uart_0 => nios_uart_txd_o, + + -- the_epcs_controller + data0_to_the_epcs_controller => config_data0_i, + dclk_from_the_epcs_controller => config_dclk_o, + sce_from_the_epcs_controller => config_ce_n_o, + sdo_from_the_epcs_controller => config_asd0_o + ); +--@} +end rtl; diff --git a/lib/altera/cyc3_pll_0ns.qip b/lib/altera/cyc3_pll_0ns.qip new file mode 100644 index 0000000..b5fc63e --- /dev/null +++ b/lib/altera/cyc3_pll_0ns.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "8.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "cyc3_pll_0ns.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3_pll_0ns.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3_pll_0ns.ppf"] diff --git a/lib/altera/cyc3_pll_0ns.vhd b/lib/altera/cyc3_pll_0ns.vhd new file mode 100644 index 0000000..6ef53f9 --- /dev/null +++ b/lib/altera/cyc3_pll_0ns.vhd @@ -0,0 +1,351 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: cyc3_pll_0ns.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.0 Build 215 05/29/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY cyc3_pll_0ns IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); +END cyc3_pll_0ns; + + +ARCHITECTURE SYN OF cyc3_pll_0ns IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire4_bv(0 DOWNTO 0) <= "0"; + sub_wire4 <= To_stdlogicvector(sub_wire4_bv); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + sub_wire2 <= inclk0; + sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=cyc3_pll_0ns", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "Fast", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire3, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "cyc3_pll_0ns.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "Fast" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns.vhd TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns.ppf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns.inc FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns.cmp TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns.bsf FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns_inst.vhd FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns_waveforms.html TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_0ns_wave*.jpg FALSE FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/lib/altera/cyc3_pll_m3ns.qip b/lib/altera/cyc3_pll_m3ns.qip new file mode 100644 index 0000000..0a32086 --- /dev/null +++ b/lib/altera/cyc3_pll_m3ns.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "8.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "cyc3_pll_m3ns.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3_pll_m3ns.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3_pll_m3ns.ppf"] diff --git a/lib/altera/cyc3_pll_m3ns.vhd b/lib/altera/cyc3_pll_m3ns.vhd new file mode 100644 index 0000000..0643ce0 --- /dev/null +++ b/lib/altera/cyc3_pll_m3ns.vhd @@ -0,0 +1,351 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: cyc3_pll_m3ns.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.0 Build 215 05/29/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY cyc3_pll_m3ns IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); +END cyc3_pll_m3ns; + + +ARCHITECTURE SYN OF cyc3_pll_m3ns IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire4_bv(0 DOWNTO 0) <= "0"; + sub_wire4 <= To_stdlogicvector(sub_wire4_bv); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + sub_wire2 <= inclk0; + sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "-3000", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=cyc3_pll_m3ns", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "Fast", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire3, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "cyc3_pll_m3ns.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "Fast" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns.vhd TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns.ppf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns.inc FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns.cmp TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns.bsf FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns_inst.vhd FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns_waveforms.html TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL cyc3_pll_m3ns_wave*.jpg FALSE FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/lib/altera/cyc3pll_eth_phy.qip b/lib/altera/cyc3pll_eth_phy.qip new file mode 100644 index 0000000..3ec98fd --- /dev/null +++ b/lib/altera/cyc3pll_eth_phy.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "8.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "cyc3pll_eth_phy.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3pll_eth_phy.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cyc3pll_eth_phy.ppf"] diff --git a/lib/altera/sinet_pll.qip b/lib/altera/sinet_pll.qip new file mode 100644 index 0000000..8fc5037 --- /dev/null +++ b/lib/altera/sinet_pll.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "8.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sinet_pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sinet_pll.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sinet_pll.ppf"] diff --git a/lib/altera/sinet_pll.vhd b/lib/altera/sinet_pll.vhd new file mode 100644 index 0000000..a9c3abf --- /dev/null +++ b/lib/altera/sinet_pll.vhd @@ -0,0 +1,444 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: sinet_pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.0 Build 215 05/29/2008 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY sinet_pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END sinet_pll; + + +ARCHITECTURE SYN OF sinet_pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 2, + clk1_duty_cycle => 50, + clk1_multiply_by => 1, + clk1_phase_shift => "0", + clk2_divide_by => 4, + clk2_duty_cycle => 50, + clk2_multiply_by => 1, + clk2_phase_shift => "0", + clk3_divide_by => 1, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "-3000", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=sinet_pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "Fast", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-3.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "sinet_pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-3000" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "Fast" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll.vhd TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll.ppf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll.inc FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll.cmp TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll.bsf FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll_inst.vhd FALSE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll_waveforms.html TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL sinet_pll_wave*.jpg FALSE FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/lib/misc/components/reset_sync.vhd b/lib/misc/components/reset_sync.vhd new file mode 100644 index 0000000..27c1e78 --- /dev/null +++ b/lib/misc/components/reset_sync.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------ +-- _____ ______ _____ - +-- |_ _| | ____|/ ____| Institute of Embedded Systems - +-- | | _ __ | |__ | (___ Zuercher Hochschule fuer - +-- | | | '_ \| __| \___ \ angewandte Wissenschaften - +-- _| |_| | | | |____ ____) | (University of Applied Sciences) - +-- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - +------------------------------------------------------------------ +-- +-- Project : SInet +-- Module : synthesis library ines_misc +-- Description : reset synchronisytion +-- +-- $LastChangedDate: 2008-10-31 12:06:00 +0100 (Fri, 31 Oct 2008) $ +-- $Rev: 1905 $ +-- $Author: ffar $ +----------------------------------------------------------------- +-- +-- Change History +-- Date |Name |Modification +----------------------------------------------------------------- +-- 02.11.07 | ffar | file created based on library component +-- 24.06.08 | kelt | resets synchronized +----------------------------------------------------------------- + + +library ieee; + use ieee.std_logic_1164.all; + +package reset_sync_pkg is + component reset_sync + generic( + STAGES : integer := 4 + ); + port( + clk_i : in std_logic; + reset1_n_i : in std_logic; + reset2_n_i : in std_logic := '1'; + reset_n_o : out std_logic := '0' + ); + end component reset_sync; +end package reset_sync_pkg; + + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity reset_sync is + generic( + STAGES : integer := 4 + ); + port( + clk_i : in std_logic; + reset1_n_i : in std_logic; + reset2_n_i : in std_logic := '1'; + reset_n_o : out std_logic := '0' + ); +end reset_sync; + +architecture rtl of reset_sync is + + signal reset1_n_f, reset1_n_ff : std_logic; + signal reset2_n_f, reset2_n_ff : std_logic; + +begin + + reset_prc : process(clk_i) + variable count : integer range 0 to STAGES-1 := 0; + begin + if clk_i'event and clk_i = '1' then + reset1_n_f <= reset1_n_i; + reset1_n_ff <= reset1_n_f; + reset2_n_f <= reset2_n_i; + reset2_n_ff <= reset2_n_f; + if (reset1_n_ff and reset2_n_ff) = '0' then + reset_n_o <= '0'; + count := 0; + elsif count < STAGES-1 then + reset_n_o <= '0'; + count := count + 1; + else + reset_n_o <= '1'; + end if; + end if; + end process reset_prc; + +end rtl; \ No newline at end of file diff --git a/quartus/dionysos_nios2mmu.bsf b/quartus/dionysos_nios2mmu.bsf new file mode 100644 index 0000000..fb0209d --- /dev/null +++ b/quartus/dionysos_nios2mmu.bsf @@ -0,0 +1,166 @@ +(header "symbol" (version "1.1")) +(symbol +(rect 0 0 448 432) +(text "dionysos_nios2mmu" (rect 4 0 136 16)(font "Arial" (font_size 10))) +(text "inst" (rect 4 416 28 432)(font "Arial")) +(port +(pt 0 32) +(input) +(text "clk_0 " (rect 0 0 25 16)(font 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"select_n_to_the_cfi_flash_0 " (rect 0 0 134 16)(font "Arial" (font_size 8))) +(text "select_n_to_the_cfi_flash_0 " (rect 287 297 421 313)(font "Arial" (font_size 8))) +(line (pt 432 304)(pt 448 304)(line_width 1)) +) +(port +(pt 448 320) +(output) +(text "tri_state_bridge_0_address[21..0] " (rect 0 0 163 16)(font "Arial" (font_size 8))) +(text "tri_state_bridge_0_address[21..0] " (rect 257 313 421 329)(font "Arial" (font_size 8))) +(line (pt 432 320)(pt 448 320)(line_width 3)) +) +(port +(pt 448 336) +(bidir) +(text "tri_state_bridge_0_data[7..0] " (rect 0 0 139 16)(font "Arial" (font_size 8))) +(text "tri_state_bridge_0_data[7..0] " (rect 282 329 421 345)(font "Arial" (font_size 8))) +(line (pt 432 336)(pt 448 336)(line_width 3)) +) +(port +(pt 448 352) +(output) +(text "tri_state_bridge_0_readn " (rect 0 0 122 16)(font "Arial" (font_size 8))) +(text "tri_state_bridge_0_readn " (rect 299 345 421 361)(font "Arial" (font_size 8))) +(line (pt 432 352)(pt 448 352)(line_width 1)) +) +(port +(pt 448 368) +(output) +(text "write_n_to_the_cfi_flash_0 " (rect 0 0 128 16)(font "Arial" (font_size 8))) +(text "write_n_to_the_cfi_flash_0 " (rect 292 361 421 377)(font "Arial" (font_size 8))) +(line (pt 432 368)(pt 448 368)(line_width 1)) +) +(port +(pt 448 400) +(output) +(text "txd_from_the_uart_0 " (rect 0 0 98 16)(font "Arial" (font_size 8))) +(text "txd_from_the_uart_0 " (rect 322 393 421 409)(font "Arial" (font_size 8))) +(line (pt 432 400)(pt 448 400)(line_width 1)) +) +(drawing +(line (pt 16 64)(pt 431 64)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 128)(pt 431 128)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 288)(pt 431 288)(color 0 0 0)(dotted)(line_width 1)) +(line (pt 16 384)(pt 431 384)(color 0 0 0)(dotted)(line_width 1)) +(rectangle (rect 16 16 432 416)(line_width 1))) +) diff --git a/quartus/dionysos_nios2mmu.qpf b/quartus/dionysos_nios2mmu.qpf new file mode 100644 index 0000000..f89d952 --- /dev/null +++ b/quartus/dionysos_nios2mmu.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 9.1 Build 222 10/21/2009 SJ Full Version +# Date created = 17:15:51 February 22, 2010 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.1" +DATE = "17:15:51 February 22, 2010" + +# Revisions + +PROJECT_REVISION = "dionysos_nios2mmu" diff --git a/quartus/dionysos_nios2mmu.qsf b/quartus/dionysos_nios2mmu.qsf new file mode 100644 index 0000000..6f7f6be --- /dev/null +++ b/quartus/dionysos_nios2mmu.qsf @@ -0,0 +1,438 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 9.1 Build 222 10/21/2009 SJ Full Version +# Date created = 17:15:51 February 22, 2010 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# dionysos-nios2mmu_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Device assignments +# ------------------ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C40F484C6 + +# Project wide assignments +# ------------------------ +set_global_assignment -name TOP_LEVEL_ENTITY "dionysos-nios2mmu" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:15:51 FEBRUARY 22, 2010" +set_global_assignment -name LAST_QUARTUS_VERSION 9.1 +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL + +# Clock inputs +# ------------ +set_location_assignment PIN_G2 -to clock_50_i +#set_location_assignment PIN_T2 -to et_phy1_tx_clk_1_i +#set_location_assignment PIN_T1 -to et_phy1_rx_clk_1_i +#set_location_assignment PIN_G21 -to usb_clk_i +#set_location_assignment PIN_G22 -to sdfe_clk_20mhz_i +#set_location_assignment PIN_T21 -to et_phy2_rx_clk_2_i +#set_location_assignment PIN_T22 -to et_phy2_tx_clk_2_i +set_location_assignment PIN_A12 -to aux_clk_n_i +set_location_assignment PIN_B12 -to aux_clk_p_i +#set_location_assignment PIN_AB12 -to et_phy2_rx_clk_1_i +#set_location_assignment PIN_AA12 -to et_phy2_tx_clk_1_i +#set_location_assignment PIN_AB11 -to et_phy1_rx_clk_2_i +#set_location_assignment PIN_AA11 -to et_phy1_tx_clk_2_i + +# FPGA programming pins +# --------------------- +set_location_assignment PIN_E2 -to config_ce_n_o +set_location_assignment PIN_D1 -to config_asd0_o +set_location_assignment PIN_K1 -to config_data0_i +set_location_assignment PIN_K2 -to config_dclk_o + +# FPGA bank 1 +# ------------- +set_location_assignment PIN_G4 -to nios_uart_txd_o +set_location_assignment PIN_B2 -to nios_uart_rxd_i +#set_location_assignment PIN_G3 -to mstt_uart_txd_o +#set_location_assignment PIN_B1 -to mstt_uart_rxd_i +set_location_assignment PIN_G5 -to gen_led_r_o[5] +set_location_assignment PIN_E4 -to gen_led_g_o[5] +set_location_assignment PIN_E3 -to iom_du_o +set_location_assignment PIN_C2 -to iom_dd_i +set_location_assignment PIN_C1 -to iom_fsc_o +set_location_assignment PIN_D2 -to iom_dclk_o +set_location_assignment PIN_H7 -to reserve0_i +set_location_assignment PIN_J6 -to reserve1_i +#set_location_assignment PIN_E1 -to i2c_sda_io +#set_location_assignment PIN_F2 -to i2c_scl_o +set_location_assignment PIN_F1 -to gen_led_r_o[4] +set_location_assignment PIN_H8 -to gen_led_g_o[4] +set_location_assignment PIN_J5 -to switch_i[0] +set_location_assignment PIN_H5 -to switch_i[1] +set_location_assignment PIN_L8 -to switch_i[2] +set_location_assignment PIN_K8 -to switch_i[3] +set_location_assignment PIN_K7 -to gen_led_r_o[0] +set_location_assignment PIN_J4 -to gen_led_g_o[0] +set_location_assignment PIN_H2 -to gp_led_o[0] +set_location_assignment PIN_H1 -to gp_led_o[1] +set_location_assignment PIN_J3 -to gp_led_o[2] +set_location_assignment PIN_J2 -to gp_led_o[3] + +# FPGA bank 2 +# ----------- +#set_location_assignment PIN_L6 -to ssram_d_io[2] +#set_location_assignment PIN_M6 -to ssram_a_o[17] +#set_location_assignment PIN_M2 -to ssram_bwc_n_o +#set_location_assignment PIN_M1 -to ssram_bwb_n_o +#set_location_assignment PIN_M4 -to ssram_ce_n_o +#set_location_assignment PIN_M3 -to ssram_bwd_n_o +#set_location_assignment PIN_N2 -to ssram_a_o[14] +#set_location_assignment PIN_N1 -to ssram_a_o[13] +#set_location_assignment PIN_L7 -to ssram_d_io[3] +#set_location_assignment PIN_M5 -to ssram_a_o[16] +#set_location_assignment PIN_P2 -to ssram_d_io[12] +#set_location_assignment PIN_P1 -to ssram_d_io[11] +#set_location_assignment PIN_R2 -to ssram_a_o[12] +#set_location_assignment PIN_R1 -to ssram_a_o[11] +#set_location_assignment PIN_N5 -to ssram_a_o[15] +#set_location_assignment PIN_P4 -to ssram_d_io[14] +#set_location_assignment PIN_P3 -to ssram_d_io[13] +#set_location_assignment PIN_U2 -to ssram_a_o[6] +#set_location_assignment PIN_U1 -to ssram_a_o[0] +#set_location_assignment PIN_V2 -to ssram_a_o[4] +#set_location_assignment PIN_V1 -to ssram_a_o[3] +#set_location_assignment PIN_P5 -to ssram_d_io[15] +#set_location_assignment PIN_N6 -to ssram_oe_n_o +#set_location_assignment PIN_M7 -to ssram_d_io[0] +#set_location_assignment PIN_M8 -to ssram_d_io[1] +#set_location_assignment PIN_N8 -to ssram_bwa_n_o +#set_location_assignment PIN_W2 -to ssram_a_o[2] +#set_location_assignment PIN_W1 -to ssram_d_io[16] +#set_location_assignment PIN_Y2 -to ssram_d_io[7] +#set_location_assignment PIN_Y1 -to ssram_d_io[6] +#set_location_assignment PIN_T3 -to ssram_a_o[7] +#set_location_assignment PIN_N7 -to ssram_we_n_o +#set_location_assignment PIN_P7 -to ssram_a_o[18] +#set_location_assignment PIN_AA2 -to ssram_d_io[5] +#set_location_assignment PIN_AA1 -to ssram_d_io[4] +#set_location_assignment PIN_V4 -to ssram_a_o[1] +#set_location_assignment PIN_V3 -to ssram_a_o[5] +#set_location_assignment PIN_P6 -to ssram_d_io[17] +#set_location_assignment PIN_T5 -to ssram_a_o[9] +#set_location_assignment PIN_T4 -to ssram_a_o[8] +#set_location_assignment PIN_R5 -to ssram_d_io[8] +#set_location_assignment PIN_R6 -to ssram_d_io[9] +#set_location_assignment PIN_R7 -to ssram_d_io[10] +#set_location_assignment PIN_T7 -to ssram_a_o[10] + +# FPGA bank 3 +# ----------- +#set_location_assignment PIN_V5 -to et_phy1_rx_dv_1_i +#set_location_assignment PIN_U7 -to et_phy1_rx_er_1_i +#set_location_assignment PIN_U8 -to et_phy1_crs_1_i +#set_location_assignment PIN_Y4 -to et_phy1_rxd_1_i[0] +#set_location_assignment PIN_Y3 -to et_phy1_rxd_1_i[1] +#set_location_assignment PIN_Y6 -to et_phy1_rxd_1_i[2] +#set_location_assignment PIN_AA3 -to ssram_clk_o +set_location_assignment PIN_AB3 -to reserve7_i +#set_location_assignment PIN_W6 -to et_phy1_rxd_1_i[3] +#set_location_assignment PIN_V7 -to et_phy1_col_1_i +#set_location_assignment PIN_AB4 -to et_phy1_tx_en_1_o +#set_location_assignment PIN_AA5 -to et_phy1_txd_1_o[0] +#set_location_assignment PIN_AB5 -to et_phy1_txd_1_o[1] +#set_location_assignment PIN_T8 -to et_phy1_txd_1_o[2] +#set_location_assignment PIN_T9 -to et_phy1_txd_1_o[3] +#set_location_assignment PIN_W7 -to et_phy1_int_1_i +set_location_assignment PIN_Y7 -to reserve2_i +#set_location_assignment PIN_U9 -to et_phy1_rx_dv_2_i +#set_location_assignment PIN_V8 -to et_phy1_rx_er_2_i +#set_location_assignment PIN_W8 -to et_phy1_crs_2_i +#set_location_assignment PIN_AA7 -to et_phy1_rxd_2_i[0] +#set_location_assignment PIN_AB7 -to et_phy1_rxd_2_i[1] +#set_location_assignment PIN_Y8 -to et_phy1_rxd_2_i[2] +#set_location_assignment PIN_T10 -to et_phy1_rxd_2_i[3] +#set_location_assignment PIN_T11 -to et_phy1_col_2_i +set_location_assignment PIN_V9 -to reserve3_i +set_location_assignment PIN_V10 -to et_phy1_tx_en_2_o +set_location_assignment PIN_U10 -to et_phy1_txd_2_o[0] +set_location_assignment PIN_AA8 -to et_phy1_txd_2_o[1] +set_location_assignment PIN_AB8 -to et_phy1_txd_2_o[2] +set_location_assignment PIN_AA9 -to et_phy1_txd_2_o[3] +set_location_assignment PIN_AB9 -to et_phy1_int_2_i +set_location_assignment PIN_U11 -to et_phy1_mdc_o +set_location_assignment PIN_V11 -to et_phy1_mdio_io +#set_location_assignment PIN_W10 -to rst_et_phy1_n_o +set_location_assignment PIN_Y10 -to gen_led_r_o[3] +set_location_assignment PIN_AA10 -to gen_led_g_o[3] + +# FPGA bank 4 +# ----------- +#set_location_assignment PIN_AA13 -to otg_d_io[0] +#set_location_assignment PIN_AB13 -to otg_d_io[1] +#set_location_assignment PIN_AA14 -to otg_d_io[2] +#set_location_assignment PIN_AB14 -to otg_d_io[3] +#set_location_assignment PIN_V12 -to otg_d_io[4] +#set_location_assignment PIN_W13 -to otg_d_io[5] +#set_location_assignment PIN_Y13 -to otg_d_io[6] +#set_location_assignment PIN_AA15 -to otg_d_io[7] +#set_location_assignment PIN_AB15 -to otg_d_io[8] +#set_location_assignment PIN_U12 -to otg_d_io[9] +#set_location_assignment PIN_AA16 -to otg_d_io[10] +#set_location_assignment PIN_AB16 -to otg_d_io[11] +#set_location_assignment PIN_T12 -to otg_d_io[12] +#set_location_assignment PIN_T13 -to otg_d_io[13] +#set_location_assignment PIN_V13 -to otg_d_io[14] +#set_location_assignment PIN_W14 -to otg_d_io[15] +#set_location_assignment PIN_U13 -to otg_a_o[0] +#set_location_assignment PIN_V14 -to otg_a_o[1] +#set_location_assignment PIN_U14 -to otg_cs_n_o +#set_location_assignment PIN_U15 -to otg_we_n_o +#set_location_assignment PIN_V15 -to otg_oe_n_o +#set_location_assignment PIN_W15 -to otg_int0_i +#set_location_assignment PIN_T14 -to otg_int1_i +#set_location_assignment PIN_T15 -to otg_reset_n_o +#set_location_assignment PIN_AB18 -to otg_dreq0_i +#set_location_assignment PIN_AA17 -to otg_dreq1_i +#set_location_assignment PIN_AB17 -to otg_dack0_n_o +#set_location_assignment PIN_AA18 -to otg_dack1_n_o +#set_location_assignment PIN_AB19 -to et_phy2_rx_dv_1_i +set_location_assignment PIN_W17 -to gen_led_r_o[6] +#set_location_assignment PIN_Y17 -to et_phy2_tx_en_1_o +set_location_assignment PIN_AB20 -to gen_led_r_o[2] +set_location_assignment PIN_V16 -to gen_led_g_o[2] +set_location_assignment PIN_U16 -to reserve4_i +set_location_assignment PIN_U17 -to reserve5_i +set_location_assignment PIN_T16 -to aux_clk_p_o +set_location_assignment PIN_R16 -to aux_clk_n_o +set_location_assignment PIN_R15 -to gen_led_g_o[6] + +# FPGA bank 5 +# ----------- +#set_location_assignment PIN_AA22 -to et_phy2_txd_2_o[3] +#set_location_assignment PIN_AA21 -to et_phy2_txd_2_o[2] +#set_location_assignment PIN_T17 -to et_phy2_txd_2_o[1] +#set_location_assignment PIN_T18 -to et_phy2_txd_2_o[0] +#set_location_assignment PIN_W20 -to et_phy2_txd_1_o[3] +#set_location_assignment PIN_W19 -to et_phy2_txd_1_o[2] +#set_location_assignment PIN_Y22 -to et_phy2_txd_1_o[1] +#set_location_assignment PIN_Y21 -to et_phy2_txd_1_o[0] +#set_location_assignment PIN_U20 -to et_phy2_rxd_2_i[3] +#set_location_assignment PIN_U19 -to et_phy2_rxd_2_i[2] +#set_location_assignment PIN_W22 -to et_phy2_rxd_2_i[1] +#set_location_assignment PIN_W21 -to et_phy2_rxd_2_i[0] +#set_location_assignment PIN_P15 -to et_phy2_rxd_1_i[3] +#set_location_assignment PIN_P16 -to et_phy2_rxd_1_i[2] +#set_location_assignment PIN_R17 -to et_phy2_rxd_1_i[1] +#set_location_assignment PIN_P17 -to et_phy2_rxd_1_i[0] +#set_location_assignment PIN_V22 -to et_phy2_rx_er_1_i +#set_location_assignment PIN_V21 -to et_phy2_crs_2_i +#set_location_assignment PIN_R20 -to rst_et_phy2_n_o +#set_location_assignment PIN_U22 -to et_phy2_rx_er_2_i +#set_location_assignment PIN_U21 -to et_phy2_col_2_i +#set_location_assignment PIN_R18 -to et_phy2_crs_1_i +#set_location_assignment PIN_R19 -to et_phy2_col_1_i +#set_location_assignment PIN_N16 -to mpd_io[0] +#set_location_assignment PIN_R22 -to mpd_io[1] +#set_location_assignment PIN_R21 -to mpd_io[2] +#set_location_assignment PIN_P20 -to mpd_io[3] +#set_location_assignment PIN_P22 -to mpd_io[4] +#set_location_assignment PIN_P21 -to mpd_io[5] +#set_location_assignment PIN_N20 -to mpd_io[6] +#set_location_assignment PIN_N19 -to mpd_io[7] +set_location_assignment PIN_N18 -to reserve6_i +set_location_assignment PIN_N21 -to fpga_reset_n_i +#set_location_assignment PIN_M22 -to et_phy2_rx_dv_2_i +#set_location_assignment PIN_M21 -to et_phy2_tx_en_2_o +#set_location_assignment PIN_AA20 -to et_phy2_int_1_i +#set_location_assignment PIN_M20 -to et_phy2_int_2_i +#set_location_assignment PIN_M19 -to et_phy2_mdc_o +#set_location_assignment PIN_M16 -to et_phy2_mdio_io + +# FPGA bank 6 +# ----------- +set_location_assignment PIN_L22 -to flash_a_o[2] +set_location_assignment PIN_L21 -to flash_a_o[4] +set_location_assignment PIN_K19 -to fash_acc_o +set_location_assignment PIN_K22 -to flash_a_o[6] +set_location_assignment PIN_K21 -to flash_a_o[18] +set_location_assignment PIN_J22 -to flash_a_o[12] +set_location_assignment PIN_J21 -to flash_a_o[14] +set_location_assignment PIN_H22 -to flash_a_o[13] +set_location_assignment PIN_H21 -to flash_a_o[11] +set_location_assignment PIN_K17 -to flash_a_o[9] +set_location_assignment PIN_K18 -to flash_we_n_o +set_location_assignment PIN_J18 -to flash_a_o[16] +set_location_assignment PIN_F22 -to flash_oe_n_o +set_location_assignment PIN_F21 -to flash_d_io[1] +set_location_assignment PIN_H20 -to flash_a_o[8] +set_location_assignment PIN_H19 -to flash_reset_n_o +set_location_assignment PIN_E22 -to flash_a_o[10] +set_location_assignment PIN_E21 -to flash_a_o[20] +set_location_assignment PIN_H18 -to flash_a_o[7] +set_location_assignment PIN_J17 -to flash_a_o[15] +set_location_assignment PIN_H16 -to flash_a_o[3] +set_location_assignment PIN_D22 -to flash_a_o[17] +set_location_assignment PIN_D21 -to flash_a_o[19] +set_location_assignment PIN_F20 -to flash_d_io[3] +set_location_assignment PIN_F19 -to flash_d_io[4] +set_location_assignment PIN_G18 -to flash_a_o[1] +set_location_assignment PIN_H17 -to flash_a_o[5] +set_location_assignment PIN_C22 -to flash_d_io[5] +set_location_assignment PIN_C21 -to flash_a_o[21] +set_location_assignment PIN_B22 -to flash_d_io[0] +set_location_assignment PIN_B21 -to flash_a_o[0] +set_location_assignment PIN_C20 -to flash_d_io[2] +set_location_assignment PIN_D20 -to flash_d_io[7] +set_location_assignment PIN_F17 -to flash_d_io[6] +set_location_assignment PIN_G17 -to flash_ce_n_o + +# FPGA bank 7 +# ----------- +set_location_assignment PIN_F16 -to dram_a_o[0] +set_location_assignment PIN_E16 -to dram_a_o[1] +set_location_assignment PIN_F15 -to dram_a_o[2] +set_location_assignment PIN_G16 -to dram_a_o[3] +set_location_assignment PIN_G15 -to dram_a_o[4] +set_location_assignment PIN_F14 -to dram_a_o[5] +set_location_assignment PIN_H15 -to dram_a_o[6] +set_location_assignment PIN_H14 -to dram_a_o[7] +set_location_assignment PIN_D17 -to dram_a_o[8] +set_location_assignment PIN_C19 -to dram_a_o[9] +set_location_assignment PIN_D19 -to dram_a_o[10] +set_location_assignment PIN_A20 -to dram_a_o[11] +set_location_assignment PIN_B20 -to dram_clk_o +set_location_assignment PIN_C17 -to dram_d_io[0] +set_location_assignment PIN_B19 -to dram_d_io[1] +set_location_assignment PIN_A19 -to dram_d_io[2] +set_location_assignment PIN_A18 -to dram_d_io[3] +set_location_assignment PIN_B18 -to dram_d_io[4] +set_location_assignment PIN_D15 -to dram_d_io[5] +set_location_assignment PIN_E15 -to dram_d_io[6] +set_location_assignment PIN_G14 -to dram_d_io[7] +set_location_assignment PIN_G13 -to dram_d_io[8] +set_location_assignment PIN_A17 -to dram_d_io[9] +set_location_assignment PIN_B17 -to dram_d_io[10] +set_location_assignment PIN_A16 -to dram_d_io[11] +set_location_assignment PIN_B16 -to dram_d_io[12] +set_location_assignment PIN_C15 -to dram_d_io[13] +set_location_assignment PIN_E14 -to dram_d_io[14] +set_location_assignment PIN_F13 -to dram_d_io[15] +set_location_assignment PIN_B15 -to dram_cke_o +set_location_assignment PIN_C13 -to dram_ldqm_o +set_location_assignment PIN_D13 -to dram_udqm_o +set_location_assignment PIN_E13 -to dram_we_n_o +set_location_assignment PIN_A14 -to dram_cas_n_o +set_location_assignment PIN_B14 -to dram_ras_n_o +set_location_assignment PIN_A13 -to dram_cs_n_o +set_location_assignment PIN_B13 -to dram_ba0_n_o +set_location_assignment PIN_E12 -to dram_ba1_n_o +set_location_assignment PIN_F11 -to dram_a_o[12] + +# FPGA bank 8 +# ----------- +#set_location_assignment PIN_D10 -to sdfe_dout_0_i +#set_location_assignment PIN_E10 -to sdfe_din_0_o +#set_location_assignment PIN_A10 -to sdfe_aux_0_0_o +#set_location_assignment PIN_B10 -to sdfe_aux_0_1_o +#set_location_assignment PIN_A9 -to sdfe_aux_0_2_o +#set_location_assignment PIN_B9 -to sdfe_aux_0_3_i +#set_location_assignment PIN_C10 -to sdfe_aux_0_4_i +#set_location_assignment PIN_G11 -to sdfe_aux_0_5_i +#set_location_assignment PIN_A8 -to sdfe_refclk_0_i +set_location_assignment PIN_B8 -to reserve8_i +#set_location_assignment PIN_B7 -to sdfe_dout_3_i +#set_location_assignment PIN_A6 -to sdfe_din_3_o +#set_location_assignment PIN_B6 -to sdfe_aux_3_0_o +#set_location_assignment PIN_E9 -to sdfe_aux_3_1_o +#set_location_assignment PIN_C8 -to sdfe_aux_3_2_o +#set_location_assignment PIN_C7 -to sdfe_aux_3_3_i +#set_location_assignment PIN_H11 -to sdfe_aux_3_4_i +#set_location_assignment PIN_H10 -to sdfe_aux_3_5_i +#set_location_assignment PIN_A5 -to sdfe_refclk_3_i +set_location_assignment PIN_B5 -to gen_led_r_o[1] +set_location_assignment PIN_G10 -to gen_led_g_o[1] +#set_location_assignment PIN_F10 -to sdfe_scdi_o +#set_location_assignment PIN_C6 -to sdfe_scdo_i +#set_location_assignment PIN_D7 -to sdfe_scck_o +#set_location_assignment PIN_A4 -to rst_sdfe_n_o +#set_location_assignment PIN_B4 -to mprdy_n_io +#set_location_assignment PIN_F8 -to mpcs_n_o +#set_location_assignment PIN_G8 -to mpwr_n_o +#set_location_assignment PIN_A3 -to mprd_n_o +#set_location_assignment PIN_B3 -to mpint_n_i +#set_location_assignment PIN_D6 -to mpclk_o +#set_location_assignment PIN_E7 -to isdn_cs_n_o +#set_location_assignment PIN_C3 -to mpad_o[0] +#set_location_assignment PIN_C4 -to mpad_o[1] +#set_location_assignment PIN_F7 -to mpad_o[2] +#set_location_assignment PIN_G7 -to mpad_o[3] +#set_location_assignment PIN_F9 -to mpad_o[4] +#set_location_assignment PIN_E5 -to et_phy_clk_50mhz_o + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" + +set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_reset_n_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reserve8_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_r_o[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_g_o[1] + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name QUARTUS_PTF_FILE dionysos_nios2mmu.ptf +set_global_assignment -name SOPC_FILE dionysos_nios2mmu.sopc +set_global_assignment -name SOURCE_FILE dionysos_nios2mmu.sopcinfo +set_global_assignment -name VHDL_FILE dionysos_nios2mmu.vhd +set_global_assignment -name VHDL_FILE ../lib/misc/components/reset_sync.vhd +set_global_assignment -name VHDL_FILE ../dionysos_top.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/quartus/dionysos_nios2mmu.sdc b/quartus/dionysos_nios2mmu.sdc new file mode 100644 index 0000000..a4948ef --- /dev/null +++ b/quartus/dionysos_nios2mmu.sdc @@ -0,0 +1,202 @@ +## +## DEVICE "EP3C40F484C6" +## + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clock_50} -period 20.000 [get_ports {clock_50_i}] + +# Write and Read Clock for the EPCS16N-98364 device +#---------------------- +create_clock -name epcs_wd_clk -period 25MHz [get_ports config_dclk_o] +create_clock -name epcs_rd_clk -period 20MHz -add [get_ports config_dclk_o] + +# JTAG: constrain the TCK port [Quartus II TimeQuest Timing Analyzer Cookbook] +#----------------------------------------------------------------------------- +#create_clock -name tck -period 10MHz [get_ports altera_reserved_tck] + +#************************************************************** +# Create Generated Clock (Used for Clock relations (PLL)) +#************************************************************** + +# connected via PLL (Normal Mode, -3ns phase shift +create_generated_clock -name pll_1_clk_3 -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|inclk[0]}] \ + -phase -54.000 [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[3]}] + +create_generated_clock -name clock_dram -source [get_pins {sinet_pll|altpll_component|auto_generated|pll1|clk[3]}] \ + [get_ports {dram_clk_o}] + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + +# EPCS16N-98364 (EPCS): cut all paths between the write and read clock (just one of both is active at any time) +set_clock_groups -asynchronous -group [get_clocks epcs_wd_clk] -group [get_clocks epcs_rd_clk] -group [get_clocks {pll_1_clk_0}] + +# JTAG: cut all paths to and from tck +#set_clock_groups -asynchronous -group [get_clocks tck] + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +set_clock_uncertainty -from { pll_1_clk_0 } -to { pll_1_clk_0 } 0.2 +set_clock_uncertainty -from { pll_1_clk_0 } -to { pll_1_clk_1 } 0.2 +set_clock_uncertainty -from { pll_1_clk_0 } -to { clock_dram } 0.2 + +set_clock_uncertainty -from { pll_1_clk_1 } -to { pll_1_clk_1 } 0.2 +set_clock_uncertainty -from { pll_1_clk_1 } -to { pll_1_clk_0 } 0.2 + +set_clock_uncertainty -from { pll_1_clk_2 } -to { pll_1_clk_2 } 0.2 +set_clock_uncertainty -from { pll_1_clk_2 } -to { pll_1_clk_0 } 0.2 + +set_clock_uncertainty -from { et_phy_clk } -to { pll_1_clk_0 } 0.2 + +set_clock_uncertainty -from { clock_dram } -to { clock_dram } 0.2 +set_clock_uncertainty -from { clock_dram } -to { pll_1_clk_0 } 0.2 + +set_clock_uncertainty -from { clock_ssram } -to { pll_1_clk_0 } 0.2 + +#************************************************************** +# Set Input Delay +#************************************************************** + +# SDRAM Timing Constraints IS42S16800D-7TL +#------------------- +# CAS Latency (Latency = 3), Access Time From CLK: t_AC = 6.5 ns +set_input_delay -max -clock [get_clocks {clock_dram}] 6.500 [get_ports {dram_d_io[*]}] +# CAS Latency (Latency = 3), Output Data Hold Time: t_OH = 2.7 ns +set_input_delay -min -clock [get_clocks {clock_dram}] 2.700 [get_ports {dram_d_io[*]}] + +# EPCS16N-98364 (EPCS) +#------------------- +# Read Operation Timing, Clock Falling Edge to Data: t_nCLK2D = 15 ns (FROM FALLING CLOCK EDGE) +set_input_delay -max -clock_fall -clock epcs_rd_clk 15.000 [get_ports {config_data0_i}] +# Read Operation Timing, Output Hold time is not known, therfore we chosse 0 ns (FROM FALLING CLOCK EDGE) +set_input_delay -min -clock_fall -clock epcs_rd_clk 0.000 [get_ports {config_data0_i}] + +# JTAG: constrain the TDI and TMS port [Quartus II TimeQuest Timing Analyzer Cookbook] +#------------------------------------------------------------------------------------- +#set_input_delay -clock tck 20 \ +# [get_ports altera_reserved_tdi] +#set_input_delay -clock tck 20 \ +# [get_ports altera_reserved_tms] + +#************************************************************** +# Set Output Delay +#************************************************************** + +# SDRAM Timing Constraints IS42S16800D-7TL +#------------------- +# Address/Input Data/CKE/COMMAND Setup Time: t_AS, t_DS, t_CKS, t_CS = 1.5 ns +set_output_delay -max -clock [get_clocks {clock_dram}] 1.500 [get_ports {dram_a_o[*] dram_d_io[*] \ + dram_cke_o dram_ba?_n_o dram_cs_n_o \ + dram_ras_n_o dram_cas_n_o dram_we_n_o dram_ldqm_o dram_udqm_o}] +# Address/Input Data/CKE/COMMAND Hold Time: t_AH, t_DH, t_CKH, t_CH = 0.8 ns +set_output_delay -min -clock [get_clocks {clock_dram}] -0.800 [get_ports {dram_a_o[*] dram_d_io[*] \ + dram_cke_o dram_ba?_n_o dram_cs_n_o \ + dram_ras_n_o dram_cas_n_o dram_we_n_o dram_ldqm_o dram_udqm_o}] + +# EPCS16N-98364 (EPCS) +#------------------- +# Write Operation Timing, Data In Setup time: t_DSU = 5 ns +set_output_delay -max -clock epcs_wd_clk 5.000 [get_ports config_asd0_o] +# Write Operation Timing, Data In Hold time: t_DH = 5 ns +set_output_delay -min -clock epcs_wd_clk -5.000 [get_ports config_asd0_o] + +# Write Operation Timing, Chip select Setup time: t_NCSSU = 10 ns +set_output_delay -max -clock epcs_wd_clk 10.000 [get_ports config_ce_n_o] + +# Write Operation Timing, Chip select Hold time: t_NCSH = 10 ns +set_output_delay -min -clock epcs_wd_clk -10.000 [get_ports config_ce_n_o] + +# JTAG: constrain the TDO port [Quartus II TimeQuest Timing Analyzer Cookbook] +#----------------------------------------------------------------------------- +#set_output_delay -clock tck 20 \ +# [get_ports altera_reserved_tdo] + +#************************************************************** +# Set False Path +#************************************************************** + +# Main input reset +#------------------- +set_false_path -from [get_ports {fpga_reset_n_i}] + +# NIOS CPU +#------------------- +# Nios uart signals (RS232) +set_false_path -from [get_ports {nios_uart_rxd_i}] +set_false_path -to [get_ports {nios_uart_txd_o}] + +# GP-LEDs +#------------------- +set_false_path -to [get_ports {gp_led_o[*] gen_led_g_o[*] gen_led_r_o[*]}] + +# Switch Input +#------------------- +set_false_path -from [get_ports {switch_i[*]}] + +# Reserve Pins +#------------------- +set_false_path -from [get_ports {reserve?_i}] + +# Parallel Flash (S29AL032D 70TF100) +# timing is to do in SOPC System +#------------------- +set_false_path -from [get_ports {flash_d_io[*]}] +set_false_path -to [get_ports {flash_d_io[*] flash_a_o[*] flash_we_n_o flash_reset_n_o flash_oe_n_o flash_ce_n_o fash_acc_o}] + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +# compensate the negative phase shift of the output SDRAM clock for hold check +# clock_50 ___|----|____|----| +# clock_dram_pll __|----|____|----| +# Compensate setup path from clock_50 to clock_dram_pll +set_multicycle_path -from [get_clocks pll_1_clk_0] \ + -to [get_clocks clock_dram] \ + -setup -end 1 + +# Compensate hold path from clock_dram_pll to clock_50 (default sdc configuration) +set_multicycle_path -from [get_clocks pll_1_clk_0] \ + -to [get_clocks clock_dram] \ + -hold -start 0 + +# clock_dram_pll __|----|____|----| +# clock_50 ___|----|____|----| +# Compensate setup path from clock_dram_pll to clock_50 +set_multicycle_path -from [get_clocks clock_dram] \ + -to [get_clocks pll_1_clk_0] \ + -setup -start 2 + +# Hold is already correct and has not to be defined + +#set_multicycle_path -from [get_clocks {clock_50}] \ +# -to [get_fanouts [get_registers {clk_50_en}]] \ +# -hold -end 1 + +#************************************************************** +# Set Input Transition +#************************************************************** + + +#************************************************************** +# Set Load +#************************************************************** diff --git a/quartus/dionysos_nios2mmu.sopc b/quartus/dionysos_nios2mmu.sopc new file mode 100644 index 0000000..6bbc587 --- /dev/null +++ b/quartus/dionysos_nios2mmu.sopc @@ -0,0 +1,566 @@ + + + + + + + + dionysos-nios2mmu.qpf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + cpu_0.jtag_debug_module + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + s1/address,s1/data,s1/read_n + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + INTERACTIVE_ASCII_OUTPUT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/quartus/dionysos_nios2mmu.sopcinfo b/quartus/dionysos_nios2mmu.sopcinfo new file mode 100644 index 0000000..f3c2e42 --- /dev/null +++ b/quartus/dionysos_nios2mmu.sopcinfo @@ -0,0 +1,9792 @@ + + + + + + + com.altera.entityinterfaces.moduleext.IDeviceFamily$EDeviceFamily + CYCLONEIII + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage + VHDL + false + true + true + true + + + java.lang.String + dionysos-nios2mmu.qpf + false + true + true + true + + + long + -19653124377 + false + true + true + true + + + long + 1269273057814 + false + true + true + true + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + clk_in + false + true + false + true + + + long + 50000000 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + reset_n_out + Output + 1 + reset_n + + + clk_out + Output + 1 + clk + + + false + cpu_0 + clk + cpu_0.clk + + + false + sdram_0 + clk + sdram_0.clk + + + false + tri_state_bridge_0 + clk + tri_state_bridge_0.clk + + + false + cfi_flash_0 + clk + cfi_flash_0.clk + + + false + epcs_flash_controller_0 + clk + epcs_flash_controller_0.clk + + + false + timer_0 + clk + timer_0.clk + + + false + uart_0 + clk + uart_0.clk + + + false + jtag_uart_0 + clk + jtag_uart_0.clk + + + false + onchip_memory2_0 + clk1 + onchip_memory2_0.clk1 + + + false + onchip_memory2_0 + clk2 + onchip_memory2_0.clk2 + + + + + + java.lang.Long + 0 + true + true + false + true + + + java.lang.Boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + in_clk + Input + 1 + clk + + + in_reset_n + Input + 1 + reset_n + + + + + + + embeddedsw.configuration.cpuArchitecture + Nios II + + + embeddedsw.configuration.HDLSimCachesCleared + 1 + + + embeddedsw.CMacro.CPU_IMPLEMENTATION + "fast" + + + embeddedsw.CMacro.BIG_ENDIAN + 0 + + + embeddedsw.CMacro.CPU_FREQ + 50000000u + + + embeddedsw.CMacro.ICACHE_LINE_SIZE + 32 + + + embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2 + 5 + + + embeddedsw.CMacro.ICACHE_SIZE + 4096 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE + 32 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2 + 5 + + + embeddedsw.CMacro.DCACHE_SIZE + 2048 + + + embeddedsw.CMacro.INITDA_SUPPORTED + + + + embeddedsw.CMacro.FLUSHDA_SUPPORTED + + + + embeddedsw.CMacro.HAS_JMPI_INSTRUCTION + + + + embeddedsw.configuration.resetSlave + cfi_flash_0.s1 + + + embeddedsw.configuration.resetOffset + 0 + + + embeddedsw.configuration.exceptionSlave + sdram_0.s1 + + + embeddedsw.configuration.exceptionOffset + 32 + + + embeddedsw.configuration.breakSlave + cpu_0.jtag_debug_module + + + embeddedsw.configuration.breakOffset + 32 + + + embeddedsw.CMacro.MMU_PRESENT + + + + embeddedsw.CMacro.KERNEL_REGION_BASE + 0xc0000000 + + + embeddedsw.CMacro.IO_REGION_BASE + 0xe0000000 + + + embeddedsw.CMacro.KERNEL_MMU_REGION_BASE + 0x80000000 + + + embeddedsw.CMacro.USER_REGION_BASE + 0x0 + + + embeddedsw.CMacro.PROCESS_ID_NUM_BITS + 8 + + + embeddedsw.CMacro.TLB_NUM_WAYS + 16 + + + embeddedsw.CMacro.TLB_NUM_WAYS_LOG2 + 4 + + + embeddedsw.CMacro.TLB_PTR_SZ + 8 + + + embeddedsw.CMacro.TLB_NUM_ENTRIES + 256 + + + embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR + 0xc0001000 + + + embeddedsw.configuration.mmu_TLBMissExcSlave + onchip_memory2_0.s1 + + + embeddedsw.configuration.mmu_TLBMissExcOffset + 0 + + + embeddedsw.CMacro.EXCEPTION_ADDR + 0xc1000020 + + + embeddedsw.CMacro.RESET_ADDR + 0xc2400000 + + + embeddedsw.CMacro.BREAK_ADDR + 0xc2801020 + + + embeddedsw.CMacro.HAS_DEBUG_STUB + + + + embeddedsw.CMacro.HAS_DEBUG_CORE + 1 + + + embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION + + + + embeddedsw.CMacro.HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION + + + + embeddedsw.CMacro.HAS_EXTRA_EXCEPTION_INFO + + + + embeddedsw.CMacro.CPU_ID_SIZE + 1 + + + embeddedsw.CMacro.CPU_ID_VALUE + 0x0 + + + embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT + 0 + + + embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT + 1 + + + embeddedsw.CMacro.HARDWARE_MULX_PRESENT + 0 + + + embeddedsw.CMacro.INST_ADDR_WIDTH + 26 + + + embeddedsw.CMacro.DATA_ADDR_WIDTH + 26 + + + embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS + 0 + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + com.altera.nios2.components.Nios2InternalSettings$OptPerfCounterWidth + _32 + false + false + true + true + + + com.altera.nios2.components.Nios2InternalSettings$OptInterruptControllerType + Internal + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.nios2.components.Nios2InternalSettings$OptBranchPredictionType + Automatic + false + true + true + true + + + boolean + true + false + false + true + true + + + boolean + false + false + true + true + true + + + com.altera.nios2.components.Nios2InternalSettings$OptBhtPtrSz + _8 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + cfi_flash_0.s1 + false + true + true + true + + + long + 0 + false + true + true + true + + + com.altera.nios2.components.Nios2MultiplierDivider$OptMultiplier + EmbeddedMulFast + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + int + 8 + false + false + true + true + + + int + 8 + false + false + true + true + + + com.altera.nios2.components.Nios2MPU$OptRegionSize + _12 + false + false + true + true + + + com.altera.nios2.components.Nios2MPU$OptRegionSize + _12 + false + false + true + true + + + boolean + false + false + false + true + true + + + com.altera.nios2.components.Nios2MMU$OptTlbNumEntries + _4 + false + true + true + true + + + com.altera.nios2.components.Nios2MMU$OptTlbNumEntries + _6 + false + true + true + true + + + com.altera.nios2.components.Nios2MMU$OptTlbPtrSz + _7 + false + false + true + true + + + com.altera.nios2.components.Nios2MMU$OptTlbNumWays + _16 + false + true + true + true + + + com.altera.nios2.components.Nios2MMU$OptProcessIDNumBits + _8 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + onchip_memory2_0.s1 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.nios2.components.INios2Component$Impl + Fast + false + true + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptBytes + _4096 + false + true + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptRamBlockType + Automatic + false + true + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptNumTCM + _1 + false + true + true + true + + + com.altera.nios2.components.Nios2ICache$OptBurstType + None + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + sdram_0.s1 + false + true + true + true + + + long + 32 + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.nios2.components.Nios2Debug$OptLevel + Level1 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + true + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.nios2.components.Nios2Debug$OptOCIOnchipTrace + _128 + false + false + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptBytes + _2048 + false + true + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptRamBlockType + Automatic + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptNumTCM + _1 + false + true + true + true + + + com.altera.nios2.components.Nios2DCache$OptLineSize + _32 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + long + 0 + false + false + true + true + + + long + 50000000 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + cpu_0.jtag_debug_module + false + false + true + true + + + long + 32 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.Long + 50000000 + true + true + false + true + + + java.lang.Boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + i_address + Output + 26 + address + + + i_read + Output + 1 + read + + + i_readdata + Input + 32 + readdata + + + i_readdatavalid + Input + 1 + readdatavalid + + + i_waitrequest + Input + 1 + waitrequest + + + false + cpu_0 + jtag_debug_module + cpu_0.jtag_debug_module + 41947136 + 2048 + + + false + sdram_0 + s1 + sdram_0.s1 + 16777216 + 16777216 + + + false + cfi_flash_0 + s1 + cfi_flash_0.s1 + 37748736 + 4194304 + + + false + epcs_flash_controller_0 + epcs_control_port + epcs_flash_controller_0.epcs_control_port + 41949184 + 2048 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + icm0_address + Output + 26 + address + + + icm0_read + Output + 1 + read + + + icm0_readdata + Input + 32 + readdata + + + icm0_readdatavalid + Input + 1 + readdatavalid + + + icm0_waitrequest + Input + 1 + waitrequest + + + icm0_clken + Output + 1 + clken + + + false + onchip_memory2_0 + s1 + onchip_memory2_0.s1 + 4096 + 1024 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + d_address + Output + 26 + address + + + d_byteenable + Output + 4 + byteenable + + + d_read + Output + 1 + read + + + d_readdata + Input + 32 + readdata + + + d_readdatavalid + Input + 1 + readdatavalid + + + d_waitrequest + Input + 1 + waitrequest + + + d_write + Output + 1 + write + + + d_writedata + Output + 32 + writedata + + + jtag_debug_module_debugaccess_to_roms + Output + 1 + debugaccess + + + false + cpu_0 + jtag_debug_module + cpu_0.jtag_debug_module + 41947136 + 2048 + + + false + sdram_0 + s1 + sdram_0.s1 + 16777216 + 16777216 + + + false + cfi_flash_0 + s1 + cfi_flash_0.s1 + 37748736 + 4194304 + + + false + epcs_flash_controller_0 + epcs_control_port + epcs_flash_controller_0.epcs_control_port + 41949184 + 2048 + + + false + timer_0 + s1 + timer_0.s1 + 41951232 + 32 + + + false + uart_0 + s1 + uart_0.s1 + 41951264 + 32 + + + false + jtag_uart_0 + avalon_jtag_slave + jtag_uart_0.avalon_jtag_slave + 41951296 + 8 + + + + + + com.altera.entityinterfaces.IConnectionPoint + cpu_0.data_master + false + true + true + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + d_irq + Input + 32 + irq + + + false + epcs_flash_controller_0 + irq + epcs_flash_controller_0.irq + 1 + + + false + timer_0 + irq + timer_0.irq + 0 + + + false + uart_0 + irq + uart_0.irq + 2 + + + false + jtag_uart_0 + irq + jtag_uart_0.irq + 3 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + dcm0_address + Output + 26 + address + + + dcm0_byteenable + Output + 4 + byteenable + + + dcm0_clken + Output + 1 + clken + + + dcm0_read + Output + 1 + read + + + dcm0_readdata + Input + 32 + readdata + + + dcm0_readdatavalid + Input + 1 + readdatavalid + + + dcm0_waitrequest + Input + 1 + waitrequest + + + dcm0_write + Output + 1 + write + + + dcm0_writedata + Output + 32 + writedata + + + false + onchip_memory2_0 + s2 + onchip_memory2_0.s2 + 0 + 1024 + + + + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.hideDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 2048 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + jtag_debug_module_address + Input + 9 + address + + + jtag_debug_module_begintransfer + Input + 1 + begintransfer + + + jtag_debug_module_byteenable + Input + 4 + byteenable + + + jtag_debug_module_debugaccess + Input + 1 + debugaccess + + + jtag_debug_module_readdata + Output + 32 + readdata + + + jtag_debug_module_resetrequest + Output + 1 + resetrequest + + + jtag_debug_module_select + Input + 1 + chipselect + + + jtag_debug_module_write + Input + 1 + write + + + jtag_debug_module_writedata + Input + 32 + writedata + + + + + + java.lang.String + + true + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + true + + dataa + Output + 32 + dataa + + + datab + Output + 32 + datab + + + result + Input + 32 + result + + + clk_en + Output + 1 + clk_en + + + reset + Output + 1 + reset + + + start + Output + 1 + start + + + done + Input + 1 + done + + + n + Output + 8 + n + + + a + Output + 5 + a + + + b + Output + 5 + b + + + c + Output + 5 + c + + + readra + Output + 1 + readra + + + readrb + Output + 1 + readrb + + + writerc + Output + 1 + writerc + + + + + + + embeddedsw.CMacro.REGISTER_DATA_IN + 1 + + + embeddedsw.CMacro.SIM_MODEL_BASE + 1 + + + embeddedsw.CMacro.SDRAM_DATA_WIDTH + 16 + + + embeddedsw.CMacro.SDRAM_ADDR_WIDTH + 23 + + + embeddedsw.CMacro.SDRAM_ROW_WIDTH + 12 + + + embeddedsw.CMacro.SDRAM_COL_WIDTH + 9 + + + embeddedsw.CMacro.SDRAM_NUM_CHIPSELECTS + 1 + + + embeddedsw.CMacro.SDRAM_NUM_BANKS + 4 + + + embeddedsw.CMacro.REFRESH_PERIOD + 15.625 + + + embeddedsw.CMacro.POWERUP_DELAY + 100.0 + + + embeddedsw.CMacro.CAS_LATENCY + 3 + + + embeddedsw.CMacro.T_RFC + 70.0 + + + embeddedsw.CMacro.T_RP + 20.0 + + + embeddedsw.CMacro.T_MRD + 3 + + + embeddedsw.CMacro.T_RCD + 20.0 + + + embeddedsw.CMacro.T_AC + 5.5 + + + embeddedsw.CMacro.T_WR + 14.0 + + + embeddedsw.CMacro.INIT_REFRESH_COMMANDS + 2 + + + embeddedsw.CMacro.INIT_NOP_DELAY + 0.0 + + + embeddedsw.CMacro.SHARED_DATA + 0 + + + embeddedsw.CMacro.STARVATION_INDICATOR + 0 + + + embeddedsw.CMacro.TRISTATE_BRIDGE_SLAVE + "" + + + embeddedsw.CMacro.IS_INITIALIZED + 1 + + + embeddedsw.CMacro.SDRAM_BANK_WIDTH + 2 + + + embeddedsw.CMacro.CONTENTS_INFO + "" + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 16 + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + double + 5.5 + false + true + true + true + + + long + 3 + false + true + true + true + + + double + 20.0 + false + true + true + true + + + double + 70.0 + false + true + true + true + + + double + 20.0 + false + true + true + true + + + double + 14.0 + false + true + true + true + + + int + 3 + false + true + true + true + + + long + 50000000 + false + true + true + true + + + int + 9 + false + true + true + true + + + int + 16 + false + true + true + true + + + boolean + true + false + true + true + true + + + double + 0.0 + false + true + true + true + + + int + 2 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + false + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonSDRAMController.ModelMangler$PresetModels + custom + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 100.0 + false + true + true + true + + + double + 15.625 + false + true + true + true + + + boolean + true + false + true + true + true + + + int + 12 + false + true + true + true + + + long + 16777216 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.Long + 50000000 + true + true + false + true + + + java.lang.Boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isMemoryDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 16777216 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 7 + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + az_addr + Input + 23 + address + + + az_be_n + Input + 2 + byteenable_n + + + az_cs + Input + 1 + chipselect + + + az_data + Input + 16 + writedata + + + az_rd_n + Input + 1 + read_n + + + az_wr_n + Input + 1 + write_n + + + za_data + Output + 16 + readdata + + + za_valid + Output + 1 + readdatavalid + + + za_waitrequest + Output + 1 + waitrequest + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + zs_addr + Output + 12 + export + + + zs_ba + Output + 2 + export + + + zs_cas_n + Output + 1 + export + + + zs_cke + Output + 1 + export + + + zs_cs_n + Output + 1 + export + + + zs_dq + Output + 16 + export + + + zs_dqm + Output + 2 + export + + + zs_ras_n + Output + 1 + export + + + zs_we_n + Output + 1 + export + + + + + + + boolean + true + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 1 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + tri_state_bridge_0.tristate_master + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_tristate + true + + false + cfi_flash_0 + s1 + cfi_flash_0.s1 + 37748736 + 4194304 + + + + + + + embeddedsw.CMacro.SETUP_VALUE + 40 + + + embeddedsw.CMacro.WAIT_VALUE + 160 + + + embeddedsw.CMacro.HOLD_VALUE + 40 + + + embeddedsw.CMacro.TIMING_UNITS + "ns" + + + embeddedsw.CMacro.SIZE + 4194304u + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 8 + + + embeddedsw.memoryInfo.HAS_BYTE_LANE + 0 + + + embeddedsw.memoryInfo.IS_FLASH + 1 + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.GENERATE_FLASH + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.FLASH_INSTALL_DIR + APP_DIR + + + double + 40.0 + true + true + true + true + + + double + 40.0 + true + true + true + true + + + double + 160.0 + true + true + true + true + + + int + 22 + false + true + true + true + + + long + 50000000 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonCommonFlashInterface.FlashCorePresets + CUSTOM + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 40 + false + true + true + true + + + int + 40 + false + true + true + true + + + [Ljava.lang.String; + s1/address,s1/data,s1/read_n + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonCommonFlashInterface.FlashTimingUnits + NS + false + true + true + true + + + int + 160 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.Long + 50000000 + true + true + false + true + + + java.lang.Boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + + + + embeddedsw.configuration.isNonVolatileStorage + 1 + + + embeddedsw.configuration.isFlash + 1 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 4194304 + true + true + false + true + + + boolean + false + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 40 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 160 + false + true + false + true + + + int + 160 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 40 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Nanoseconds + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 160 + false + true + false + true + + + int + 160 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_tristate + false + + data + Bidir + 8 + data + + + address + Input + 22 + address + + + read_n + Input + 1 + read_n + + + write_n + Input + 1 + write_n + + + select_n + Input + 1 + chipselect_n + + + + + + + embeddedsw.CMacro.REGISTER_OFFSET + 1024 + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.MEM_INIT_FILENAME + epcs_flash_controller_0_boot_rom + + + embeddedsw.memoryInfo.IS_EPCS + 1 + + + embeddedsw.memoryInfo.IS_FLASH + 1 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.GENERATE_FLASH + 1 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.FLASH_INSTALL_DIR + APP_DIR + + + boolean + true + false + true + true + true + + + java.lang.String + Cyclone III + false + true + false + true + + + boolean + false + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isNonVolatileStorage + 1 + + + embeddedsw.configuration.isFlash + 1 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 2048 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 9 + address + + + chipselect + Input + 1 + chipselect + + + dataavailable + Output + 1 + dataavailable + + + endofpacket + Output + 1 + endofpacket + + + read_n + Input + 1 + read_n + + + readdata + Output + 32 + readdata + + + readyfordata + Output + 1 + readyfordata + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + + + + com.altera.entityinterfaces.IConnectionPoint + epcs_flash_controller_0.epcs_control_port + false + true + true + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + dclk + Output + 1 + export + + + sce + Output + 1 + export + + + sdo + Output + 1 + export + + + data0 + Input + 1 + export + + + + + + + embeddedsw.CMacro.ALWAYS_RUN + 0 + + + embeddedsw.CMacro.FIXED_PERIOD + 0 + + + embeddedsw.CMacro.SNAPSHOT + 1 + + + embeddedsw.CMacro.PERIOD + 1 + + + embeddedsw.CMacro.PERIOD_UNITS + "ms" + + + embeddedsw.CMacro.RESET_OUTPUT + 0 + + + embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT + 0 + + + embeddedsw.CMacro.FREQ + 50000000u + + + embeddedsw.CMacro.LOAD_VALUE + 49999ULL + + + embeddedsw.CMacro.COUNTER_SIZE + 32 + + + embeddedsw.CMacro.MULT + 0.0010 + + + embeddedsw.CMacro.TICKS_PER_SEC + 1000u + + + boolean + false + false + true + true + true + + + int + 32 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.AlteraAvalonTimer$TimerPeriodUnit + MSEC + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.TimerPresets + CUSTOM + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.Long + 50000000 + true + true + false + true + + + java.lang.Boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isTimerDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + writedata + Input + 16 + writedata + + + readdata + Output + 16 + readdata + + + chipselect + Input + 1 + chipselect + + + write_n + Input + 1 + write_n + + + + + + com.altera.entityinterfaces.IConnectionPoint + timer_0.s1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.BAUD + 115200 + + + embeddedsw.CMacro.DATA_BITS + 8 + + + embeddedsw.CMacro.FIXED_BAUD + 1 + + + embeddedsw.CMacro.PARITY + 'N' + + + embeddedsw.CMacro.STOP_BITS + 1 + + + embeddedsw.CMacro.SYNC_REG_DEPTH + 2 + + + embeddedsw.CMacro.USE_CTS_RTS + 0 + + + embeddedsw.CMacro.USE_EOP_REGISTER + 0 + + + embeddedsw.CMacro.SIM_TRUE_BAUD + 0 + + + embeddedsw.CMacro.SIM_CHAR_STREAM + "" + + + embeddedsw.CMacro.FREQ + 50000000u + + + int + 115200 + false + true + true + true + + + double + 0.01 + true + true + true + true + + + long + 50000000 + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonUART.AlteraAvalonUART$UartParity + NONE + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 2 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.Long + 50000000 + true + true + false + true + + + java.lang.Boolean + true + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + begintransfer + Input + 1 + begintransfer + + + chipselect + Input + 1 + chipselect + + + read_n + Input + 1 + read_n + + + write_n + Input + 1 + write_n + + + writedata + Input + 16 + writedata + + + readdata + Output + 16 + readdata + + + dataavailable + Output + 1 + dataavailable + + + readyfordata + Output + 1 + readyfordata + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + rxd + Input + 1 + export + + + txd + Output + 1 + export + + + + + + com.altera.entityinterfaces.IConnectionPoint + uart_0.s1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.WRITE_DEPTH + 64 + + + embeddedsw.CMacro.READ_DEPTH + 64 + + + embeddedsw.CMacro.WRITE_THRESHOLD + 8 + + + embeddedsw.CMacro.READ_THRESHOLD + 8 + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 64 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonJtagUART.AlteraAvalonJtagUART$JtagSimulationOptions + INTERACTIVE_ASCII_OUTPUT + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 64 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + rst_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 2 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + av_chipselect + Input + 1 + chipselect + + + av_address + Input + 1 + address + + + av_read_n + Input + 1 + read_n + + + av_readdata + Output + 32 + readdata + + + av_write_n + Input + 1 + write_n + + + av_writedata + Input + 32 + writedata + + + av_waitrequest + Output + 1 + waitrequest + + + dataavailable + Output + 1 + dataavailable + + + readyfordata + Output + 1 + readyfordata + + + + + + com.altera.entityinterfaces.IConnectionPoint + jtag_uart_0.avalon_jtag_slave + false + true + true + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + av_irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE + 0 + + + embeddedsw.CMacro.INIT_CONTENTS_FILE + "onchip_memory2_0" + + + embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED + 0 + + + embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE + "Automatic" + + + embeddedsw.CMacro.WRITABLE + 1 + + + embeddedsw.CMacro.DUAL_PORT + 1 + + + embeddedsw.CMacro.SIZE_VALUE + 1024u + + + embeddedsw.CMacro.SIZE_MULTIPLE + 1 + + + embeddedsw.CMacro.CONTENTS_INFO + "" + + + embeddedsw.CMacro.RAM_BLOCK_TYPE + "Auto" + + + embeddedsw.CMacro.INIT_MEM_CONTENT + 1 + + + embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR + 0 + + + embeddedsw.CMacro.INSTANCE_ID + "NONE" + + + embeddedsw.CMacro.READ_DURING_WRITE_MODE + "DONT_CARE" + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.HAS_BYTE_LANE + 0 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + QPF_DIR + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonOnchipMemory.AlteraAvalonOnchipMemory$BlockType + AUTO + false + true + true + true + + + int + 32 + false + true + true + true + + + java.lang.String + Cyclone III + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + onchip_memory2_0 + false + false + true + true + + + java.lang.String + NONE + false + false + true + true + + + long + 1024 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonOnchipMemory.AlteraAvalonOnchipMemory$ReadDuringWriteMode + DONT_CARE + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 1 + false + true + false + true + + + long + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk1 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 1024 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 8 + address + + + chipselect + Input + 1 + chipselect + + + clken + Input + 1 + clken + + + readdata + Output + 32 + readdata + + + write + Input + 1 + write + + + writedata + Input + 32 + writedata + + + byteenable + Input + 4 + byteenable + + + + + + long + 0 + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk2 + Input + 1 + clk + + + + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 1 + false + true + false + true + + + long + 1024 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk2 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 1024 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address2 + Input + 8 + address + + + chipselect2 + Input + 1 + chipselect + + + clken2 + Input + 1 + clken + + + readdata2 + Output + 32 + readdata + + + write2 + Input + 1 + write + + + writedata2 + Input + 32 + writedata + + + byteenable2 + Input + 4 + byteenable + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + cpu_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02801000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + instruction_master + cpu_0 + jtag_debug_module + + + + int + 1 + false + true + true + true + + + long + 0x02801000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + cpu_0 + jtag_debug_module + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + sdram_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x01000000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + instruction_master + sdram_0 + s1 + + + + int + 1 + false + true + true + true + + + long + 0x01000000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + sdram_0 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + tri_state_bridge_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x0000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + instruction_master + tri_state_bridge_0 + avalon_slave + + + + int + 1 + false + true + true + true + + + long + 0x0000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + tri_state_bridge_0 + avalon_slave + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + cfi_flash_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02400000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + tri_state_bridge_0 + tristate_master + cfi_flash_0 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + epcs_flash_controller_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02801800 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + instruction_master + epcs_flash_controller_0 + epcs_control_port + + + + int + 1 + false + true + true + true + + + long + 0x02801800 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + epcs_flash_controller_0 + epcs_control_port + + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + d_irq + epcs_flash_controller_0 + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + timer_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02802000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + timer_0 + s1 + + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + d_irq + timer_0 + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + uart_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02802020 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + uart_0 + s1 + + + + int + 2 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + d_irq + uart_0 + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + jtag_uart_0 + clk + + + + int + 1 + false + true + true + true + + + long + 0x02802040 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + data_master + jtag_uart_0 + avalon_jtag_slave + + + + int + 3 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + d_irq + jtag_uart_0 + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + onchip_memory2_0 + clk1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + onchip_memory2_0 + clk2 + + + + int + 1 + false + true + true + true + + + long + 0x1000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + tightly_coupled_instruction_master_0 + onchip_memory2_0 + s1 + + + + int + 1 + false + true + true + true + + + long + 0x0000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu_0 + tightly_coupled_data_master_0 + onchip_memory2_0 + s2 + + + 1 + altera_avalon_new_sdram_controller + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + SDRAM Controller + 9.1 + + + 1 + altera_avalon_cfi_flash + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Flash Memory Interface (CFI) + 9.1 + + + 1 + nios_custom_instruction_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Custom Instruction Master + 9.1 + + + 4 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 9.1 + + + 4 + interrupt + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Interrupt Connection + 9.1 + + + 10 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 9.1 + + + 11 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 9.1 + + + 1 + altera_avalon_timer + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Interval Timer + 9.1 + + + 1 + altera_avalon_tri_state_bridge + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Avalon-MM Tristate Bridge + 9.1 + + + 1 + avalon_tristate + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Tristate Connection + 9.1 + + + 1 + avalon_tristate_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Tristate Slave + 9.1 + + + 4 + avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Master + 9.1 + + + 9 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 9.1 + + + 1 + interrupt_receiver + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 9.1 + + + 1 + altera_nios2 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Nios II Processor + 9.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 9.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 9.1 + + + 1 + altera_avalon_onchip_memory2 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + On-Chip Memory (RAM or ROM) + 9.1 + + + 1 + altera_avalon_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + UART (RS-232 Serial Port) + 9.1 + + + 1 + altera_avalon_epcs_flash_controller + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + EPCS Serial Flash Controller + 9.1 + + + 1 + avalon_tristate_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Tristate Master + 9.1 + + + 1 + altera_avalon_jtag_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + JTAG UART + 9.1 + + + 13 + avalon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection + 6.1 + + + 3 + conduit + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit Endpoint + 7.1 + + 9.1 222 + 0023AE674DE00000012786918231 + diff --git a/quartus/dionysos_sinet.qsf b/quartus/dionysos_sinet.qsf new file mode 100644 index 0000000..0a82daa --- /dev/null +++ b/quartus/dionysos_sinet.qsf @@ -0,0 +1,639 @@ +set_global_assignment -name TOP_LEVEL_ENTITY dionysos_top +# Copyright (C) 1991-2007 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# sinet_su_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + +# Set preflow scripts +# =================== +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:dionysos_version_number.tcl" + +# Project-Wide Assignments +# ======================== +set_global_assignment -name LAST_QUARTUS_VERSION 8.0 +set_global_assignment -name INCREMENTAL_COMPILATION OFF + + + +# Clock inputs +# -------------- +set_location_assignment PIN_G2 -to clock_50_i +set_location_assignment PIN_T2 -to et_phy1_tx_clk_1_i +set_location_assignment PIN_T1 -to et_phy1_rx_clk_1_i +set_location_assignment PIN_G21 -to usb_clk_i +set_location_assignment PIN_G22 -to sdfe_clk_20mhz_i +set_location_assignment PIN_T21 -to et_phy2_rx_clk_2_i +set_location_assignment PIN_T22 -to et_phy2_tx_clk_2_i +set_location_assignment PIN_A12 -to aux_clk_n_i +set_location_assignment PIN_B12 -to aux_clk_p_i +set_location_assignment PIN_AB12 -to et_phy2_rx_clk_1_i +set_location_assignment PIN_AA12 -to et_phy2_tx_clk_1_i +set_location_assignment PIN_AB11 -to et_phy1_rx_clk_2_i +set_location_assignment PIN_AA11 -to et_phy1_tx_clk_2_i + +# FPGA programming pins +# --------------------- +set_location_assignment PIN_E2 -to config_ce_n_o +set_location_assignment PIN_D1 -to config_asd0_o +set_location_assignment PIN_K1 -to config_data0_i +set_location_assignment PIN_K2 -to config_dclk_o + +# FPGA bank 1 +# ------------- +set_location_assignment PIN_G4 -to nios_uart_txd_o +set_location_assignment PIN_B2 -to nios_uart_rxd_i +set_location_assignment PIN_G3 -to mstt_uart_txd_o +set_location_assignment PIN_B1 -to mstt_uart_rxd_i +set_location_assignment PIN_G5 -to gen_led_r_o[5] +set_location_assignment PIN_E4 -to gen_led_g_o[5] +set_location_assignment PIN_E3 -to iom_du_o +set_location_assignment PIN_C2 -to iom_dd_i +set_location_assignment PIN_C1 -to iom_fsc_o +set_location_assignment PIN_D2 -to iom_dclk_o +set_location_assignment PIN_H7 -to reserve0_i +set_location_assignment PIN_J6 -to reserve1_i +set_location_assignment PIN_E1 -to i2c_sda_io +set_location_assignment PIN_F2 -to i2c_scl_o +set_location_assignment PIN_F1 -to gen_led_r_o[4] +set_location_assignment PIN_H8 -to gen_led_g_o[4] +set_location_assignment PIN_J5 -to switch_i[0] +set_location_assignment PIN_H5 -to switch_i[1] +set_location_assignment PIN_L8 -to switch_i[2] +set_location_assignment PIN_K8 -to switch_i[3] +set_location_assignment PIN_K7 -to gen_led_r_o[0] +set_location_assignment PIN_J4 -to gen_led_g_o[0] +set_location_assignment PIN_H2 -to gp_led_o[0] +set_location_assignment PIN_H1 -to gp_led_o[1] +set_location_assignment PIN_J3 -to gp_led_o[2] +set_location_assignment PIN_J2 -to gp_led_o[3] + +# FPGA bank 2 +# ------------- +set_location_assignment PIN_L6 -to ssram_d_io[2] +set_location_assignment PIN_M6 -to ssram_a_o[17] +set_location_assignment PIN_M2 -to ssram_bwc_n_o +set_location_assignment PIN_M1 -to ssram_bwb_n_o +set_location_assignment PIN_M4 -to ssram_ce_n_o +set_location_assignment PIN_M3 -to ssram_bwd_n_o +set_location_assignment PIN_N2 -to ssram_a_o[14] +set_location_assignment PIN_N1 -to ssram_a_o[13] +set_location_assignment PIN_L7 -to ssram_d_io[3] +set_location_assignment PIN_M5 -to ssram_a_o[16] +set_location_assignment PIN_P2 -to ssram_d_io[12] +set_location_assignment PIN_P1 -to ssram_d_io[11] +set_location_assignment PIN_R2 -to ssram_a_o[12] +set_location_assignment PIN_R1 -to ssram_a_o[11] +set_location_assignment PIN_N5 -to ssram_a_o[15] +set_location_assignment PIN_P4 -to ssram_d_io[14] +set_location_assignment PIN_P3 -to ssram_d_io[13] +set_location_assignment PIN_U2 -to ssram_a_o[6] +set_location_assignment PIN_U1 -to ssram_a_o[0] +set_location_assignment PIN_V2 -to ssram_a_o[4] +set_location_assignment PIN_V1 -to ssram_a_o[3] +set_location_assignment PIN_P5 -to ssram_d_io[15] +set_location_assignment PIN_N6 -to ssram_oe_n_o +set_location_assignment PIN_M7 -to ssram_d_io[0] +set_location_assignment PIN_M8 -to ssram_d_io[1] +set_location_assignment PIN_N8 -to ssram_bwa_n_o +set_location_assignment PIN_W2 -to ssram_a_o[2] +set_location_assignment PIN_W1 -to ssram_d_io[16] +set_location_assignment PIN_Y2 -to ssram_d_io[7] +set_location_assignment PIN_Y1 -to ssram_d_io[6] +set_location_assignment PIN_T3 -to ssram_a_o[7] +set_location_assignment PIN_N7 -to ssram_we_n_o +set_location_assignment PIN_P7 -to ssram_a_o[18] +set_location_assignment PIN_AA2 -to ssram_d_io[5] +set_location_assignment PIN_AA1 -to ssram_d_io[4] +set_location_assignment PIN_V4 -to ssram_a_o[1] +set_location_assignment PIN_V3 -to ssram_a_o[5] +set_location_assignment PIN_P6 -to ssram_d_io[17] +set_location_assignment PIN_T5 -to ssram_a_o[9] +set_location_assignment PIN_T4 -to ssram_a_o[8] +set_location_assignment PIN_R5 -to ssram_d_io[8] +set_location_assignment PIN_R6 -to ssram_d_io[9] +set_location_assignment PIN_R7 -to ssram_d_io[10] +set_location_assignment PIN_T7 -to ssram_a_o[10] + +# FPGA bank 3 +# ------------- +set_location_assignment PIN_V5 -to et_phy1_rx_dv_1_i +set_location_assignment PIN_U7 -to et_phy1_rx_er_1_i +set_location_assignment PIN_U8 -to et_phy1_crs_1_i +set_location_assignment PIN_Y4 -to et_phy1_rxd_1_i[0] +set_location_assignment PIN_Y3 -to et_phy1_rxd_1_i[1] +set_location_assignment PIN_Y6 -to et_phy1_rxd_1_i[2] +set_location_assignment PIN_AA3 -to ssram_clk_o +set_location_assignment PIN_AB3 -to reserve7_i +set_location_assignment PIN_W6 -to et_phy1_rxd_1_i[3] +set_location_assignment PIN_V7 -to et_phy1_col_1_i +set_location_assignment PIN_AB4 -to et_phy1_tx_en_1_o +set_location_assignment PIN_AA5 -to et_phy1_txd_1_o[0] +set_location_assignment PIN_AB5 -to et_phy1_txd_1_o[1] +set_location_assignment PIN_T8 -to et_phy1_txd_1_o[2] +set_location_assignment PIN_T9 -to et_phy1_txd_1_o[3] +set_location_assignment PIN_W7 -to et_phy1_int_1_i +set_location_assignment PIN_Y7 -to reserve2_i +set_location_assignment PIN_U9 -to et_phy1_rx_dv_2_i +set_location_assignment PIN_V8 -to et_phy1_rx_er_2_i +set_location_assignment PIN_W8 -to et_phy1_crs_2_i +set_location_assignment PIN_AA7 -to et_phy1_rxd_2_i[0] +set_location_assignment PIN_AB7 -to et_phy1_rxd_2_i[1] +set_location_assignment PIN_Y8 -to et_phy1_rxd_2_i[2] +set_location_assignment PIN_T10 -to et_phy1_rxd_2_i[3] +set_location_assignment PIN_T11 -to et_phy1_col_2_i +set_location_assignment PIN_V9 -to reserve3_i +set_location_assignment PIN_V10 -to et_phy1_tx_en_2_o +set_location_assignment PIN_U10 -to et_phy1_txd_2_o[0] +set_location_assignment PIN_AA8 -to et_phy1_txd_2_o[1] +set_location_assignment PIN_AB8 -to et_phy1_txd_2_o[2] +set_location_assignment PIN_AA9 -to et_phy1_txd_2_o[3] +set_location_assignment PIN_AB9 -to et_phy1_int_2_i +set_location_assignment PIN_U11 -to et_phy1_mdc_o +set_location_assignment PIN_V11 -to et_phy1_mdio_io +set_location_assignment PIN_W10 -to rst_et_phy1_n_o +set_location_assignment PIN_Y10 -to gen_led_r_o[3] +set_location_assignment PIN_AA10 -to gen_led_g_o[3] + +# FPGA bank 4 +# ------------- +set_location_assignment PIN_AA13 -to otg_d_io[0] +set_location_assignment PIN_AB13 -to otg_d_io[1] +set_location_assignment PIN_AA14 -to otg_d_io[2] +set_location_assignment PIN_AB14 -to otg_d_io[3] +set_location_assignment PIN_V12 -to otg_d_io[4] +set_location_assignment PIN_W13 -to otg_d_io[5] +set_location_assignment PIN_Y13 -to otg_d_io[6] +set_location_assignment PIN_AA15 -to otg_d_io[7] +set_location_assignment PIN_AB15 -to otg_d_io[8] +set_location_assignment PIN_U12 -to otg_d_io[9] +set_location_assignment PIN_AA16 -to otg_d_io[10] +set_location_assignment PIN_AB16 -to otg_d_io[11] +set_location_assignment PIN_T12 -to otg_d_io[12] +set_location_assignment PIN_T13 -to otg_d_io[13] +set_location_assignment PIN_V13 -to otg_d_io[14] +set_location_assignment PIN_W14 -to otg_d_io[15] +set_location_assignment PIN_U13 -to otg_a_o[0] +set_location_assignment PIN_V14 -to otg_a_o[1] +set_location_assignment PIN_U14 -to otg_cs_n_o +set_location_assignment PIN_U15 -to otg_we_n_o +set_location_assignment PIN_V15 -to otg_oe_n_o +set_location_assignment PIN_W15 -to otg_int0_i +set_location_assignment PIN_T14 -to otg_int1_i +set_location_assignment PIN_T15 -to otg_reset_n_o +set_location_assignment PIN_AB18 -to otg_dreq0_i +set_location_assignment PIN_AA17 -to otg_dreq1_i +set_location_assignment PIN_AB17 -to otg_dack0_n_o +set_location_assignment PIN_AA18 -to otg_dack1_n_o +set_location_assignment PIN_AB19 -to et_phy2_rx_dv_1_i +set_location_assignment PIN_W17 -to gen_led_r_o[6] +set_location_assignment PIN_Y17 -to et_phy2_tx_en_1_o +set_location_assignment PIN_AB20 -to gen_led_r_o[2] +set_location_assignment PIN_V16 -to gen_led_g_o[2] +set_location_assignment PIN_U16 -to reserve4_i +set_location_assignment PIN_U17 -to reserve5_i +set_location_assignment PIN_T16 -to aux_clk_p_o +set_location_assignment PIN_R16 -to aux_clk_n_o +set_location_assignment PIN_R15 -to gen_led_g_o[6] + +# FPGA bank 5 +# ------------- +set_location_assignment PIN_AA22 -to et_phy2_txd_2_o[3] +set_location_assignment PIN_AA21 -to et_phy2_txd_2_o[2] +set_location_assignment PIN_T17 -to et_phy2_txd_2_o[1] +set_location_assignment PIN_T18 -to et_phy2_txd_2_o[0] +set_location_assignment PIN_W20 -to et_phy2_txd_1_o[3] +set_location_assignment PIN_W19 -to et_phy2_txd_1_o[2] +set_location_assignment PIN_Y22 -to et_phy2_txd_1_o[1] +set_location_assignment PIN_Y21 -to et_phy2_txd_1_o[0] +set_location_assignment PIN_U20 -to et_phy2_rxd_2_i[3] +set_location_assignment PIN_U19 -to et_phy2_rxd_2_i[2] +set_location_assignment PIN_W22 -to et_phy2_rxd_2_i[1] +set_location_assignment PIN_W21 -to et_phy2_rxd_2_i[0] +set_location_assignment PIN_P15 -to et_phy2_rxd_1_i[3] +set_location_assignment PIN_P16 -to et_phy2_rxd_1_i[2] +set_location_assignment PIN_R17 -to et_phy2_rxd_1_i[1] +set_location_assignment PIN_P17 -to et_phy2_rxd_1_i[0] +set_location_assignment PIN_V22 -to et_phy2_rx_er_1_i +set_location_assignment PIN_V21 -to et_phy2_crs_2_i +set_location_assignment PIN_R20 -to rst_et_phy2_n_o +set_location_assignment PIN_U22 -to et_phy2_rx_er_2_i +set_location_assignment PIN_U21 -to et_phy2_col_2_i +set_location_assignment PIN_R18 -to et_phy2_crs_1_i +set_location_assignment PIN_R19 -to et_phy2_col_1_i +set_location_assignment PIN_N16 -to mpd_io[0] +set_location_assignment PIN_R22 -to mpd_io[1] +set_location_assignment PIN_R21 -to mpd_io[2] +set_location_assignment PIN_P20 -to mpd_io[3] +set_location_assignment PIN_P22 -to mpd_io[4] +set_location_assignment PIN_P21 -to mpd_io[5] +set_location_assignment PIN_N20 -to mpd_io[6] +set_location_assignment PIN_N19 -to mpd_io[7] +set_location_assignment PIN_N18 -to reserve6_i +set_location_assignment PIN_N21 -to fpga_reset_n_i +set_location_assignment PIN_M22 -to et_phy2_rx_dv_2_i +set_location_assignment PIN_M21 -to et_phy2_tx_en_2_o +set_location_assignment PIN_AA20 -to et_phy2_int_1_i +set_location_assignment PIN_M20 -to et_phy2_int_2_i +set_location_assignment PIN_M19 -to et_phy2_mdc_o +set_location_assignment PIN_M16 -to et_phy2_mdio_io +set_global_assignment -name DEVICE EP3C40F484C6 + +# FPGA bank 6 +# ------------- +set_location_assignment PIN_L22 -to flash_a_o[2] +set_location_assignment PIN_L21 -to flash_a_o[4] +set_location_assignment PIN_K19 -to fash_acc_o +set_location_assignment PIN_K22 -to flash_a_o[6] +set_location_assignment PIN_K21 -to flash_a_o[18] +set_location_assignment PIN_J22 -to flash_a_o[12] +set_location_assignment PIN_J21 -to flash_a_o[14] +set_location_assignment PIN_H22 -to flash_a_o[13] +set_location_assignment PIN_H21 -to flash_a_o[11] +set_location_assignment PIN_K17 -to flash_a_o[9] +set_location_assignment PIN_K18 -to flash_we_n_o +set_location_assignment PIN_J18 -to flash_a_o[16] +set_location_assignment PIN_F22 -to flash_oe_n_o +set_location_assignment PIN_F21 -to flash_d_io[1] +set_location_assignment PIN_H20 -to flash_a_o[8] +set_location_assignment PIN_H19 -to flash_reset_n_o +set_location_assignment PIN_E22 -to flash_a_o[10] +set_location_assignment PIN_E21 -to flash_a_o[20] +set_location_assignment PIN_H18 -to flash_a_o[7] +set_location_assignment PIN_J17 -to flash_a_o[15] +set_location_assignment PIN_H16 -to flash_a_o[3] +set_location_assignment PIN_D22 -to flash_a_o[17] +set_location_assignment PIN_D21 -to flash_a_o[19] +set_location_assignment PIN_F20 -to flash_d_io[3] +set_location_assignment PIN_F19 -to flash_d_io[4] +set_location_assignment PIN_G18 -to flash_a_o[1] +set_location_assignment PIN_H17 -to flash_a_o[5] +set_location_assignment PIN_C22 -to flash_d_io[5] +set_location_assignment PIN_C21 -to flash_a_o[21] +set_location_assignment PIN_B22 -to flash_d_io[0] +set_location_assignment PIN_B21 -to flash_a_o[0] +set_location_assignment PIN_C20 -to flash_d_io[2] +set_location_assignment PIN_D20 -to flash_d_io[7] +set_location_assignment PIN_F17 -to flash_d_io[6] +set_location_assignment PIN_G17 -to flash_ce_n_o + +# FPGA bank 7 +# ------------- +set_location_assignment PIN_F16 -to dram_a_o[0] +set_location_assignment PIN_E16 -to dram_a_o[1] +set_location_assignment PIN_F15 -to dram_a_o[2] +set_location_assignment PIN_G16 -to dram_a_o[3] +set_location_assignment PIN_G15 -to dram_a_o[4] +set_location_assignment PIN_F14 -to dram_a_o[5] +set_location_assignment PIN_H15 -to dram_a_o[6] +set_location_assignment PIN_H14 -to dram_a_o[7] +set_location_assignment PIN_D17 -to dram_a_o[8] +set_location_assignment PIN_C19 -to dram_a_o[9] +set_location_assignment PIN_D19 -to dram_a_o[10] +set_location_assignment PIN_A20 -to dram_a_o[11] +set_location_assignment PIN_B20 -to dram_clk_o +set_location_assignment PIN_C17 -to dram_d_io[0] +set_location_assignment PIN_B19 -to dram_d_io[1] +set_location_assignment PIN_A19 -to dram_d_io[2] +set_location_assignment PIN_A18 -to dram_d_io[3] +set_location_assignment PIN_B18 -to dram_d_io[4] +set_location_assignment PIN_D15 -to dram_d_io[5] +set_location_assignment PIN_E15 -to dram_d_io[6] +set_location_assignment PIN_G14 -to dram_d_io[7] +set_location_assignment PIN_G13 -to dram_d_io[8] +set_location_assignment PIN_A17 -to dram_d_io[9] +set_location_assignment PIN_B17 -to dram_d_io[10] +set_location_assignment PIN_A16 -to dram_d_io[11] +set_location_assignment PIN_B16 -to dram_d_io[12] +set_location_assignment PIN_C15 -to dram_d_io[13] +set_location_assignment PIN_E14 -to dram_d_io[14] +set_location_assignment PIN_F13 -to dram_d_io[15] +set_location_assignment PIN_B15 -to dram_cke_o +set_location_assignment PIN_C13 -to dram_ldqm_o +set_location_assignment PIN_D13 -to dram_udqm_o +set_location_assignment PIN_E13 -to dram_we_n_o +set_location_assignment PIN_A14 -to dram_cas_n_o +set_location_assignment PIN_B14 -to dram_ras_n_o +set_location_assignment PIN_A13 -to dram_cs_n_o +set_location_assignment PIN_B13 -to dram_ba0_n_o +set_location_assignment PIN_E12 -to dram_ba1_n_o +set_location_assignment PIN_F11 -to dram_a_o[12] + +# FPGA bank 8 +# ------------- +set_location_assignment PIN_D10 -to sdfe_dout_0_i +set_location_assignment PIN_E10 -to sdfe_din_0_o +set_location_assignment PIN_A10 -to sdfe_aux_0_0_o +set_location_assignment PIN_B10 -to sdfe_aux_0_1_o +set_location_assignment PIN_A9 -to sdfe_aux_0_2_o +set_location_assignment PIN_B9 -to sdfe_aux_0_3_i +set_location_assignment PIN_C10 -to sdfe_aux_0_4_i +set_location_assignment PIN_G11 -to sdfe_aux_0_5_i +set_location_assignment PIN_A8 -to sdfe_refclk_0_i +set_location_assignment PIN_B8 -to reserve8_i +set_location_assignment PIN_B7 -to sdfe_dout_3_i +set_location_assignment PIN_A6 -to sdfe_din_3_o +set_location_assignment PIN_B6 -to sdfe_aux_3_0_o +set_location_assignment PIN_E9 -to sdfe_aux_3_1_o +set_location_assignment PIN_C8 -to sdfe_aux_3_2_o +set_location_assignment PIN_C7 -to sdfe_aux_3_3_i +set_location_assignment PIN_H11 -to sdfe_aux_3_4_i +set_location_assignment PIN_H10 -to sdfe_aux_3_5_i +set_location_assignment PIN_A5 -to sdfe_refclk_3_i +set_location_assignment PIN_B5 -to gen_led_r_o[1] +set_location_assignment PIN_G10 -to gen_led_g_o[1] +set_location_assignment PIN_F10 -to sdfe_scdi_o +set_location_assignment PIN_C6 -to sdfe_scdo_i +set_location_assignment PIN_D7 -to sdfe_scck_o +set_location_assignment PIN_A4 -to rst_sdfe_n_o +set_location_assignment PIN_B4 -to mprdy_n_io +set_location_assignment PIN_F8 -to mpcs_n_o +set_location_assignment PIN_G8 -to mpwr_n_o +set_location_assignment PIN_A3 -to mprd_n_o +set_location_assignment PIN_B3 -to mpint_n_i +set_location_assignment PIN_D6 -to mpclk_o +set_location_assignment PIN_E7 -to isdn_cs_n_o +set_location_assignment PIN_C3 -to mpad_o[0] +set_location_assignment PIN_C4 -to mpad_o[1] +set_location_assignment PIN_F7 -to mpad_o[2] +set_location_assignment PIN_G7 -to mpad_o[3] +set_location_assignment PIN_F9 -to mpad_o[4] +set_location_assignment PIN_E5 -to et_phy_clk_50mhz_o + + + + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" + +# Assembler Assignments +# ===================== + + +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to mdio_io + + + +#SOURCES +#------- +set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to et_phy2_tx_clk_2_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_reset_n_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_sdfe_n_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_0_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_1_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_2_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_3_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_4_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_0_5_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_0_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_1_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_2_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_3_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_4_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_aux_3_5_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_din_0_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_din_3_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_dout_0_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_dout_3_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_refclk_0_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_refclk_3_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_scck_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_scdi_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdfe_scdo_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reserve8_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpint_n_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mprd_n_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mprdy_n_io +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpwr_n_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to isdn_cs_n_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpad_o[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpclk_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mpcs_n_o +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_r_o[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gen_led_g_o[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to et_phy_clk_50mhz_o +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[0] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[1] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[2] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[4] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[7] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[8] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[9] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[10] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[11] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[12] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[13] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[14] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[15] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[16] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ssram_d_io[17] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 25 OHM WITHOUT CALIBRATION" -to ssram_clk_o +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE su_debug.stp +set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name QIP_FILE ../../../lib/altera/sinet_pll.qip +set_global_assignment -name VHDL_FILE ../../../lib/altera/sinet_pll.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/sinet_filter.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/prp_filter.vhd +set_global_assignment -name VHDL_FILE ../../../lib/learning_table/ip_request_to_learningtable.vhd +set_global_assignment -name VHDL_FILE ../../../lib/learning_table/address_comparator.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/arp_filter.vhd +set_global_assignment -name VHDL_FILE descriptor_memory.vhd +set_global_assignment -name VHDL_FILE sgdma_rx.vhd +set_global_assignment -name VHDL_FILE sgdma_tx.vhd +set_global_assignment -name VHDL_FILE ISP1362.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/rmii_phy_to_mii_mac.vhd +set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/su_ucom_generic_globals.vhd +set_global_assignment -name VHDL_FILE ../../../lib/misc/components/edge_det.vhd +set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/pwm_unit.vhd +set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/led_controller.vhd +set_global_assignment -name VHDL_FILE ../../../lib/learning_table/sinet_types.vhd +set_global_assignment -name VHDL_FILE ../../../lib/learning_table/learning_table.vhd +set_global_assignment -name VHDL_FILE ../../../lib/learning_table/learningtable_mng.vhd +set_global_assignment -name VHDL_FILE ../../../lib/learning_table/learningtable_ram_mng.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_rx_mux.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/dp_ram_intern.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_core_top.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_fifo.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_fifo_read_mng.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_fifo_write_mng.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_filter.vhd +set_global_assignment -name VHDL_FILE ../../../lib/ucom_core/ucom_generic_globals.vhd +set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/ucom/dsl_port_switch.vhd +set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/ucom/ucom_generic_top.vhd +set_global_assignment -name VHDL_FILE firmware_id_pkg.vhd +set_global_assignment -name SDC_FILE dionysos_sinet.sdc +set_global_assignment -name QIP_FILE nios_1.qip +set_global_assignment -name VHDL_FILE ../../../lib/bus/avalon/dm9000a_if.vhd +set_global_assignment -name VHDL_FILE nios_1_burst_3.vhd +set_global_assignment -name VHDL_FILE nios_1_burst_1.vhd +set_global_assignment -name VHDL_FILE nios_1_burst_2.vhd +set_global_assignment -name VHDL_FILE nios_1_burst_0.vhd +set_global_assignment -name VHDL_FILE cpu_0_jtag_debug_module_sysclk.vhd -library work +set_global_assignment -name VHDL_FILE cpu_0_jtag_debug_module_tck.vhd -library work +set_global_assignment -name VHDL_FILE cpu_0_jtag_debug_module_wrapper.vhd -library work +set_global_assignment -name VHDL_FILE cpu_0_mult_cell.vhd -library work +set_global_assignment -name VHDL_FILE cpu_0_test_bench.vhd -library work +set_global_assignment -name VHDL_FILE cpu_0.vhd -library work +set_global_assignment -name VHDL_FILE epcs_controller.vhd -library work +set_global_assignment -name VHDL_FILE nios_16bit_interface_wbd_1.vhd -library work +set_global_assignment -name VHDL_FILE nios_1.vhd -library work +set_global_assignment -name VHDL_FILE nios_interrupt_quirk_hdcl_rx.vhd -library work +set_global_assignment -name VHDL_FILE nios_interrupt_quirk_hdlc_tx.vhd -library work +set_global_assignment -name VHDL_FILE nios_interrupt_quirk_mac.vhd -library work +set_global_assignment -name VHDL_FILE sdram_0_test_component.vhd -library work +set_global_assignment -name VHDL_FILE sdram_0.vhd -library work +set_global_assignment -name VHDL_FILE sysid.vhd -library work +set_global_assignment -name VHDL_FILE timer_0.vhd -library work +set_global_assignment -name VHDL_FILE timer_1.vhd -library work +set_global_assignment -name VHDL_FILE uart_0.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/pck_crc16_d8.vhd -library hdlc +set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/ribu.vhd -library hdlc +set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/rx.vhd -library hdlc +set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/rx_crc.vhd -library hdlc +set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/rx_buffer.vhd -library hdlc +set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/tx.vhd -library hdlc +set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/tx_crc.vhd -library hdlc +set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/tx_buffer.vhd -library hdlc +set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/hdlc_avalon_if.vhd -library hdlc +set_global_assignment -name VHDL_FILE ../../../lib/hdlc_dsl_init/phy_init_top.vhd -library hdlc +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/uart.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/ccitt_crc_generator.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/communication_register.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_read_dfe_to_su.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_read_su_to_dfe.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_write_dfe_to_su.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dp_ram_controller_write_su_to_dfe.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/ethernet_header_plus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/frame_analyzer.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/framerasen_generator.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/priority_mux.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/rahmen_minus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/rahmen_plus.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/sequence_number_crc_generator.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/sicherungs_fsm.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/access_mux.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/dfe_connector/dfe_connector_top.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/misc/reduce_pkg.vhd -library ines_misc +set_global_assignment -name VHDL_FILE ../../../lib/misc/ines_vhdl_lib_base_pkg.vhd -library ines_misc +set_global_assignment -name VHDL_FILE ../../../lib/misc/components/register_r.vhd -library ines_misc +set_global_assignment -name VHDL_FILE ../../../lib/misc/components/buf_sync.vhd +set_global_assignment -name VHDL_FILE ../../../lib/misc/components/register_rw.vhd -library ines_misc +set_global_assignment -name VHDL_FILE ../../../lib/misc/components/bibuf_async.vhd -library ines_misc +set_global_assignment -name VHDL_FILE ../../../lib/misc/components/bibuf_sync.vhd -library ines_misc +set_global_assignment -name VHDL_FILE ../../../lib/misc/components/reset_sync.vhd -library ines_misc +set_global_assignment -name VHDL_FILE ../../../lib/misc/components/generic_sp_ram.vhd -library ines_misc +set_global_assignment -name VHDL_FILE ../../../lib/misc/components/ram.vhd -library ines_misc +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/clock_logic.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/pkg_rt_nrt_segment.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_arbit.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_flag_det.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_ser_par.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_arbit.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_flag_data_mux.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_par_ser.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rt_nrt_segment_top.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/clk_edge_det.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/rx_top.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/rt_nrt_segmentation/tx_top.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/bus/wishbone/wb_register_rw.vhd -library ines_bus +set_global_assignment -name VHDL_FILE ../../../lib/bus/avalon/avalon_multimaster_16.vhd -library ines_bus +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/ethernet_pkg.vhd -library ines_ethernet +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/prp_rct_detect.vhd -library ines_ethernet +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/crc_generator.vhd -library ines_ethernet +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/rmii_in_out.vhd -library ines_ethernet +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/mii_management_transmit.vhd -library ines_ethernet +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/mdio_interface.vhd -library ines_ethernet +set_global_assignment -name VHDL_FILE ../../../lib/ethernet/components/mac_filter.vhd -library ines_ethernet +set_global_assignment -name VHDL_FILE ../../../lib/altera/hash_ram_112.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/altera/mac_table_96.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/ram_arbiter/arbiter_pkg.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/ram_arbiter/ram_arbiter_sram.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/ram_arbiter/ram_arbiter_ssram.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_core_register_mapping.vhd +set_global_assignment -name VHDL_FILE ../../../lib/su_core/traffic_led_delay.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/learn_stw_addr.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/counter_32.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/counters.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/cpu_interface.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_queue.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_fifo.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/rx_fifo.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/hash_lookup.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/seq_count_ram.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/seq_counter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_serializer.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_filter_rules.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/mac_addr_comparator.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_mac_filter.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/rx_processing12.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/rx_processing3.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/tx_processing.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_core/su_core.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/region_global.vhd +set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/su/su_generic_top.vhd -library work +set_global_assignment -name VHDL_FILE ../../../lib/su_ucom_generic/su_ucom_generic_top.vhd -library work +set_global_assignment -name VHDL_FILE ../dionysos_top.vhd +set_global_assignment -name SIGNALTAP_FILE tx_serializer.stp +set_global_assignment -name SIGNALTAP_FILE su_input_ports.stp +set_global_assignment -name SIGNALTAP_FILE su_input_ports_neuer_su_core_und_neuer_hdlc_.stp +set_global_assignment -name SIGNALTAP_FILE su_input_ports_lange_frames_und_wenig_segmente.stp +set_global_assignment -name SIGNALTAP_FILE rmii_phy_to_mii_mac_debug.stp +set_global_assignment -name SIGNALTAP_FILE rmii_phy_to_mii_mac_debug_2.stp +set_global_assignment -name SIGNALTAP_FILE tse_mac_debug.stp +set_global_assignment -name SIGNALTAP_FILE tsgdma_debug.stp +set_global_assignment -name SIGNALTAP_FILE tse_mag_debug.stp +set_global_assignment -name SIGNALTAP_FILE su_debug.stp +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -- cgit v1.2.3-54-g00ecf