From be1f6f5f6a204e4279699b7a427c1f1c45ea338b Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 26 Mar 2010 16:21:03 +0100 Subject: Rename project, correctly instantiate SOPC system --- dionysos_top.vhd | 22 +++--- quartus/dionysos_nios2mmu.qsf | 10 ++- quartus/dionysos_nios2mmu.sopc | 38 +++++----- quartus/dionysos_nios2mmu.sopcinfo | 150 ++++++++++++++++++------------------- 4 files changed, 113 insertions(+), 107 deletions(-) diff --git a/dionysos_top.vhd b/dionysos_top.vhd index faa6b65..208b967 100644 --- a/dionysos_top.vhd +++ b/dionysos_top.vhd @@ -16,7 +16,7 @@ ------------|----------|----------------------------------------- -- 14.02.07 | kelt |file created for SInet ------------|----------|----------------------------------------- --- 22.02.10 | klto |file adjusted for dionysos-nios2mmu project +-- 22.02.10 | klto |file adjusted for dionysos_nios2mmu project ----------------------------------------------------------------- library ieee; @@ -198,12 +198,12 @@ architecture rtl of dionysos_top is --! \li EPCS Controller --! \n See \subpage nios_config_page for details - cpu : entity work.cpu_0 + dionysos_nios2mmu_inst : work.dionysos_nios2mmu port map( - clk => pll_clk_50, + clk_0 => pll_clk_50, reset_n => reset_nios_n, - -- the_sdram_0 + -- sdram_0 zs_addr_from_the_sdram_0 => dram_a_o(11 downto 0), -- dram_a_o(12) is for 32Mbit SDRAM zs_ba_from_the_sdram_0 => dram_ba, zs_cas_n_from_the_sdram_0 => dram_cas_n_o, @@ -214,22 +214,22 @@ architecture rtl of dionysos_top is zs_ras_n_from_the_sdram_0 => dram_ras_n_o, zs_we_n_from_the_sdram_0 => dram_we_n_o, - -- the_tri_state_bridge_0_avalon_slave + -- tri_state_bridge_0 select_n_to_the_cfi_flash_0 => flash_ce_n_o, tri_state_bridge_0_address => flash_a_o, tri_state_bridge_0_data => flash_d_io, tri_state_bridge_0_readn => flash_oe_n_o, write_n_to_the_cfi_flash_0 => flash_we_n_o, - -- the_uart_0 + -- uart_0 rxd_to_the_uart_0 => nios_uart_rxd_i, txd_from_the_uart_0 => nios_uart_txd_o, - -- the_epcs_controller - data0_to_the_epcs_controller => config_data0_i, - dclk_from_the_epcs_controller => config_dclk_o, - sce_from_the_epcs_controller => config_ce_n_o, - sdo_from_the_epcs_controller => config_asd0_o + -- epcs_controller + data0_to_the_epcs_flash_controller_0 => config_data0_i, + dclk_from_the_epcs_flash_controller_0 => config_dclk_o, + sce_from_the_epcs_flash_controller_0 => config_ce_n_o, + sdo_from_the_epcs_flash_controller_0 => config_asd0_o ); --@} end rtl; diff --git a/quartus/dionysos_nios2mmu.qsf b/quartus/dionysos_nios2mmu.qsf index 1d72e86..925dfed 100644 --- a/quartus/dionysos_nios2mmu.qsf +++ b/quartus/dionysos_nios2mmu.qsf @@ -25,7 +25,7 @@ # Notes: # # 1) The default values for assignments are stored in the file: -# dionysos-nios2mmu_assignment_defaults.qdf +# dionysos_nios2mmu_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -427,7 +427,13 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + +set_global_assignment -name QIP_FILE ../lib/altera/sinet_pll.qip set_global_assignment -name VHDL_FILE ../lib/misc/components/reset_sync.vhd set_global_assignment -name VHDL_FILE ../dionysos_top.vhd +set_global_assignment -name QIP_FILE dionysos_nios2mmu.qip +set_global_assignment -name VHDL_FILE dionysos_nios2mmu.vhd + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/quartus/dionysos_nios2mmu.sopc b/quartus/dionysos_nios2mmu.sopc index 6bbc587..441628a 100644 --- a/quartus/dionysos_nios2mmu.sopc +++ b/quartus/dionysos_nios2mmu.sopc @@ -19,7 +19,7 @@ } datum megawizard_uipreferences { - value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos-nios2mmu}"; + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu}"; type = "String"; } } @@ -40,7 +40,7 @@ } datum megawizard_uipreferences { - value = "{}"; + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu/quartus}"; type = "String"; } } @@ -102,27 +102,19 @@ type = "String"; } } - element onchip_memory2_0.s1 - { - datum baseAddress - { - value = "4096"; - type = "long"; - } - } - element timer_0.s1 + element cfi_flash_0.s1 { datum baseAddress { - value = "41951232"; + value = "37748736"; type = "long"; } } - element uart_0.s1 + element onchip_memory2_0.s1 { datum baseAddress { - value = "41951264"; + value = "4096"; type = "long"; } } @@ -139,11 +131,19 @@ type = "long"; } } - element cfi_flash_0.s1 + element uart_0.s1 { datum baseAddress { - value = "37748736"; + value = "41951264"; + type = "long"; + } + } + element timer_0.s1 + { + datum baseAddress + { + value = "41951232"; type = "long"; } } @@ -156,7 +156,7 @@ } datum megawizard_uipreferences { - value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos-nios2mmu}"; + value = "{output_language=VHDL, output_directory=/home/tklauser/projects/dionysos_nios2mmu}"; type = "String"; } } @@ -205,9 +205,9 @@ - dionysos-nios2mmu.qpf + dionysos_nios2mmu.qpf - + diff --git a/quartus/dionysos_nios2mmu.sopcinfo b/quartus/dionysos_nios2mmu.sopcinfo index f3c2e42..537f4d8 100644 --- a/quartus/dionysos_nios2mmu.sopcinfo +++ b/quartus/dionysos_nios2mmu.sopcinfo @@ -4,7 +4,7 @@ kind="com_altera_sopcmodel_ensemble_Ensemble" version="9.1"> - + com.altera.entityinterfaces.moduleext.IDeviceFamily$EDeviceFamily @@ -40,7 +40,7 @@ java.lang.String - dionysos-nios2mmu.qpf + dionysos_nios2mmu.qpf false true true @@ -56,7 +56,7 @@ long - 1269273057814 + 1269616531099 false true true @@ -9595,22 +9595,6 @@ parameters are a RESULT of the module parameters. --> onchip_memory2_0 s2 - - 1 - altera_avalon_new_sdram_controller - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - SDRAM Controller - 9.1 - - - 1 - altera_avalon_cfi_flash - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Flash Memory Interface (CFI) - 9.1 - 1 nios_custom_instruction_master @@ -9620,11 +9604,11 @@ parameters are a RESULT of the module parameters. --> 9.1 - 4 - interrupt_sender + 1 + altera_nios2 com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Sender + com.altera.entityinterfaces.IModule + Nios II Processor 9.1 @@ -9636,51 +9620,51 @@ parameters are a RESULT of the module parameters. --> 9.1 - 10 - clock + 1 + avalon_tristate_slave com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Clock Connection + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Tristate Slave 9.1 - 11 - clock_sink + 1 + altera_avalon_tri_state_bridge com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input + com.altera.entityinterfaces.IModule + Avalon-MM Tristate Bridge 9.1 1 - altera_avalon_timer + altera_avalon_cfi_flash com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Interval Timer + Flash Memory Interface (CFI) 9.1 1 - altera_avalon_tri_state_bridge + clock_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Avalon-MM Tristate Bridge + Clock Source 9.1 - 1 - avalon_tristate + 9 + avalon_slave com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Tristate Connection + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave 9.1 1 - avalon_tristate_slave + altera_avalon_epcs_flash_controller com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Tristate Slave + com.altera.entityinterfaces.IModule + EPCS Serial Flash Controller 9.1 @@ -9692,83 +9676,99 @@ parameters are a RESULT of the module parameters. --> 9.1 - 9 - avalon_slave + 10 + clock com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Slave + com.altera.entityinterfaces.IConnection + Clock Connection 9.1 1 - interrupt_receiver + altera_avalon_uart com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Receiver + com.altera.entityinterfaces.IModule + UART (RS-232 Serial Port) 9.1 1 - altera_nios2 + altera_avalon_jtag_uart com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Nios II Processor + JTAG UART 9.1 1 - clock_source + altera_avalon_timer com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Clock Source + Interval Timer 9.1 - 1 - clock_source + 11 + clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output + Clock Input 9.1 1 - altera_avalon_onchip_memory2 + avalon_tristate_master com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - On-Chip Memory (RAM or ROM) + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Tristate Master 9.1 1 - altera_avalon_uart + avalon_tristate com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - UART (RS-232 Serial Port) + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Tristate Connection + 9.1 + + + 4 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender 9.1 1 - altera_avalon_epcs_flash_controller + altera_avalon_onchip_memory2 com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - EPCS Serial Flash Controller + On-Chip Memory (RAM or ROM) 9.1 1 - avalon_tristate_master + interrupt_receiver com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Tristate Master + Interrupt Receiver 9.1 + + 3 + conduit + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit Endpoint + 7.1 + 1 - altera_avalon_jtag_uart + clock_source com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - JTAG UART + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output 9.1 @@ -9780,13 +9780,13 @@ parameters are a RESULT of the module parameters. --> 6.1 - 3 - conduit + 1 + altera_avalon_new_sdram_controller com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit Endpoint - 7.1 + com.altera.entityinterfaces.IModule + SDRAM Controller + 9.1 9.1 222 - 0023AE674DE00000012786918231 + 001B213B645F000001279B0ACCA1 -- cgit v1.2.3-54-g00ecf