From 014fb2a0784e4f007a7b5909de27b450b4805c77 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Tue, 2 Aug 2011 11:43:01 +0200 Subject: Regenerated dts (manually adapted for ISP1632), remove dtb --- devicetree/dionysos_nios2mmu.dts | 205 ++++++++++++++++++--------------------- 1 file changed, 92 insertions(+), 113 deletions(-) (limited to 'devicetree/dionysos_nios2mmu.dts') diff --git a/devicetree/dionysos_nios2mmu.dts b/devicetree/dionysos_nios2mmu.dts index 8dacceb..9549bc1 100644 --- a/devicetree/dionysos_nios2mmu.dts +++ b/devicetree/dionysos_nios2mmu.dts @@ -1,164 +1,143 @@ /* - * Copyright (C) 2010 Walter Goossens . - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * + * This devicetree is generated by sopc2dts + * Sopc2dts is written by Walter Goossens + * in cooperation with the nios2 community */ /dts-v1/; / { - model = "altera,dionysos_nios2mmu"; - compatible = "altera,dionysos_nios2mmu"; + model = "ALTR,dionysos_nios2mmu"; + compatible = "ALTR,dionysos_nios2mmu"; #address-cells = <1>; #size-cells = <1>; cpus { #address-cells = <1>; #size-cells = <0>; cpu_0: cpu@0x0 { - device-type = "cpu"; - compatible = "altera,nios2"; + device_type = "cpu"; + compatible = "ALTR,nios2-9.1"; reg = <0>; interrupt-controller; #interrupt-cells = <1>; - clock-frequency = <50000000>; - d-cache-block-size = <32>; - i-cache-block-size = <32>; - d-cache-size = <2048>; - i-cache-size = <4096>; + clock-frequency = <50000000>; //embeddedsw.CMacro.CPU_FREQ type NUMBER + dcache-line-size = <32>; //embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER + icache-line-size = <32>; //embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER + dcache-size = <2048>; //embeddedsw.CMacro.DCACHE_SIZE type NUMBER + icache-size = <4096>; //embeddedsw.CMacro.ICACHE_SIZE type NUMBER + ALTR,implementation = "fast"; //embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING + ALTR,pid-num-bits = <10>; //embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER + ALTR,tlb-num-ways = <16>; //embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER + ALTR,tlb-num-entries = <256>; //embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER + ALTR,tlb-ptr-sz = <8>; //embeddedsw.CMacro.TLB_PTR_SZ type NUMBER + ALTR,has-div; //embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT type NUMBER + ALTR,has-mul; //embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER + ALTR,reset-addr = <0xc4000000>; //embeddedsw.CMacro.RESET_ADDR type NUMBER + ALTR,fast-tlb-miss-addr = <0xc4802000>; //embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER + ALTR,exception-addr = <0xc0000020>; //embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER }; }; memory@0 { - device-type = "memory"; - reg = <0x01000000 0x01000000 - 0x02802000 0x00000400 - 0x04840000 0x00002000>; + device_type = "memory"; + reg = <0x00000000 0x04000000 + 0x04802000 0x00000800>; }; sopc@0 { #address-cells = <1>; #size-cells = <1>; - device-type = "soc"; - compatible = "altera,avalon","simple-bus"; + device_type = "soc"; + compatible = "ALTR,avalon","simple-bus"; ranges ; bus-frequency = < 50000000 >; //Port instruction_master of cpu_0 - epcs_flash_controller_0: flash@0x2801800 { + epcs_flash_controller_0: spi@0x5000400 { #address-cells = <1>; - #size-cells = <1>; - compatible = "altera,epcs_flash", "epcs-flash"; - reg = <0x2801800 0x800>; + #size-cells = <0>; + compatible = "ALTR,spi-9.1","ALTR,spi-1.0"; + reg = < 0x5000400 0x800>; interrupt-parent = < &cpu_0 >; - interrupts = <1>; - bank-width = <2>; - device-width = <1>; - dtb@0 { - reg = < 0x00000000 0x00020000 >; - read-only; - }; - fpga@20000 { - reg = < 0x00020000 0x00160000 >; - read-only; - }; - kernel@180000 { - reg = < 0x00180000 0x00280000 >; - read-only; - }; - rootfs@400000 { - reg = < 0x00400000 0x00C00000 >; + interrupts = < 1 >; + + m25p80@0 { + compatible = "m25p80"; + reg = <0>; }; - }; //end flash (epcs_flash_controller_0) + }; //end spi (epcs_flash_controller_0) - cfi_flash_0: flash@0x2400000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "altera,cfi_flash", "cfi-flash"; - reg = <0x2400000 0x400000>; + cfi_flash_0: flash@0x4000000 { + compatible = "ALTR,cfi_flash-9.1","cfi-flash"; + reg = < 0x4000000 0x400000>; bank-width = <1>; device-width = <1>; - dtb@0 { - reg = < 0x00000000 0x00020000 >; - read-only; - }; - fpga@20000 { - reg = < 0x00020000 0x00160000 >; - read-only; - }; - kernel@180000 { - reg = < 0x00180000 0x00280000 >; - read-only; - }; - rootfs@400000 { - reg = < 0x00400000 0x00C00000 >; - }; }; //end flash (cfi_flash_0) //Port tightly_coupled_instruction_master_0 of cpu_0 //Port data_master of cpu_0 - timer_0: unknown@0x2802880 { - compatible = "unknown,unknown"; - reg = <0x2802880 0x8>; + timer_0: timer@0x4400000 { + compatible = "ALTR,timer-9.1","ALTR,timer-1.0"; + reg = < 0x4400000 0x20>; interrupt-parent = < &cpu_0 >; - interrupts = <0>; - }; //end unknown (timer_0) + interrupts = < 0 >; + clock-frequency = <50000000>; + }; //end timer (timer_0) - uart_0: serial@0x28028a0 { - compatible = "altera,altera_uart"; - reg = <0x28028a0 0x8>; + uart_0: serial@0x6000000 { + compatible = "ALTR,uart-9.1","ALTR,uart-1.0"; + reg = < 0x6000000 0x20>; interrupt-parent = < &cpu_0 >; - interrupts = <2>; - current-speed = <115200>; - clock-frequency = <50000000>; + interrupts = < 2 >; + current-speed = <115200>; //embeddedsw.CMacro.BAUD type NUMBER + clock-frequency = <50000000>; //embeddedsw.CMacro.FREQ type NUMBER }; //end serial (uart_0) - jtag_uart_0: serial@0x28028c0 { - compatible = "altera,altera_juart"; - reg = <0x28028c0 0x2>; + jtag_uart_0: serial@0x7000000 { + compatible = "ALTR,juart-9.1","ALTR,juart-1.0"; + reg = < 0x7000000 0x8>; interrupt-parent = < &cpu_0 >; - interrupts = <3>; + interrupts = < 3 >; }; //end serial (jtag_uart_0) - tse_mac: ethernet@0x2802400 { - compatible = "altera,tse"; - reg = <0x2802400 0x400>; - altera,sgdma_tx = < &sgdma_tx >; - altera,sgdma_rx = < &sgdma_rx >; - }; //end ethernet (tse_mac) - - sgdma_rx: dma@0x2802800 { - compatible = "altera,alt_sgdma"; - reg = <0x2802800 0x40>; - interrupt-parent = < &cpu_0 >; - interrupts = <4>; - type = < 2 >; //STREAM_TO_MEMORY - }; //end dma (sgdma_rx) - - sgdma_tx: dma@0x2802840 { - compatible = "altera,alt_sgdma"; - reg = <0x2802840 0x40>; + tse_mac: ethernet@0x8002400 { + compatible = "ALTR,tse-9.1","ALTR,tse-1.0"; + reg = < 0x8002400 0x400 0x8100000 0x40 0x8200000 0x40 0x4840000 0x2000>; interrupt-parent = < &cpu_0 >; - interrupts = <5>; - type = < 1 >; //MEMORY_TO_STREAM - }; //end dma (sgdma_tx) + interrupts = < 4 5 >; + ALTR,rx-fifo-depth = <1024>; //embeddedsw.CMacro.RECEIVE_FIFO_DEPTH type NUMBER + ALTR,tx-fifo-depth = <1024>; //embeddedsw.CMacro.TRANSMIT_FIFO_DEPTH type NUMBER + address-bits = <48>; + max-frame-size = <1518>; + local-mac-address = [ 00 15 12 01 42 23 ]; + ALTR,mii-id = <0>; // manually added + ALTR,phy-addr = <2>; // manually added + }; //end ethernet (tse_mac) watchdog_timer: watchdog@0x4880000 { - compatible = "altera,altera_wdt"; - reg = <0x4880000 0x8>; + compatible = "ALTR,wdt-9.1","ALTR,wdt-1.0"; + reg = < 0x4880000 0x20>; interrupt-parent = < &cpu_0 >; - interrupts = <6>; + interrupts = < 6 >; clock-frequency = <50000000>; + timeout = <249999999>; //embeddedsw.CMacro.LOAD_VALUE type NUMBER }; //end watchdog (watchdog_timer) + sysid: sysid@0x8000000 { + compatible = "ALTR,sysid-9.1","ALTR,sysid-1.0"; + reg = < 0x8000000 0x8>; + }; //end sysid (sysid) + + ISP1362: isp1362@0x8220000 { + compatible = "nxp,usb-isp1362"; + reg = < 0x8220000 0x4 0x8220004 0x4>; // manually adjusted + interrupt-parent = < &cpu_0 >; + interrupts = < 7 8 >; + nxp,sel15Kres; +// nxp,clknotstop; +// nxp,oc_enable; +// nxp,int_act_high; +// nxp,int_edge_triggered; +// nxp,remote_wakeup_connected; + nxp,no_power_switching; +// nxp,power_switching_mode; + }; //end isp1362 (ISP1362) + //Port tightly_coupled_data_master_0 of cpu_0 }; //sopc chosen { -- cgit v1.2.3-54-g00ecf