From 267b9022dd49d0d4a2ee88044e8ff734d139a282 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Wed, 19 Jan 2011 17:21:56 +0100 Subject: Updates: Pull LEDS low, rename TSE MAC, add watchdog timer, add sysid --- dionysos_top.vhd | 96 ++++++++++++++++++++++++++++++-------------------------- 1 file changed, 52 insertions(+), 44 deletions(-) (limited to 'dionysos_top.vhd') diff --git a/dionysos_top.vhd b/dionysos_top.vhd index 66e0392..6924a30 100644 --- a/dionysos_top.vhd +++ b/dionysos_top.vhd @@ -6,9 +6,10 @@ -- _| |_| | | | |____ ____) | (University of Applied Sciences) - -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - ------------------------------------------------------------------ --- $LastChangedDate: 2008-02-06 14:28:53 +0100 (Mi, 06 Feb 2008) $ --- $Rev: 828 $ --- $Author: ffar $ +-- +-- $LastChangedDate: $ +-- $Rev: $ +-- $Author: $ ----------------------------------------------------------------- -- -- Change History @@ -200,6 +201,17 @@ architecture rtl of dionysos_top is --! FPGA main clock frequency (50MHz) constant C_FPGA_FREQ : integer := 50000000; + --! front pannel LEDs + signal leds : std_logic_vector(15 downto 0); + + --! @name SDRAM Data + --@{ + --! Nios SDRAM controller data mask (byte select) + signal dram_dqm : std_logic_vector(1 downto 0); + --! Nios SDRAM controller bank address + signal dram_ba : std_logic_vector(1 downto 0); + --@} + --! 50 MHz Clock which is Source Synchronous to the DRAM Data signal pll_clk_50 : std_logic; --! 25 MHz Clock @@ -214,16 +226,6 @@ architecture rtl of dionysos_top is signal fpga_reset_n_ff_100 : std_logic; --! Reset for the NIOS. Active in Ethernet Modus (no DSL) signal reset_nios_n : std_logic; - - --! front pannel LEDs - signal leds : std_logic_vector(15 downto 0); - - --! @name SDRAM Data - --@{ - --! Nios SDRAM controller data mask (byte select) - signal dram_dqm : std_logic_vector(1 downto 0); - --! Nios SDRAM controller bank address - signal dram_ba : std_logic_vector(1 downto 0); --@} --! @name RX byte stream interface of ethernet phy 1 @@ -263,7 +265,7 @@ architecture rtl of dionysos_top is signal et_phy2_tx_ack_2 : std_logic; --@} - --! link status of ethernet interfaces (from MDIO) \todo tidy mdio + --! link status of ethernet interfaces (from MDIO) signal et_phy1_link_status : std_logic_vector(3 downto 0); --! synchronised on clock dip switch states @@ -356,6 +358,11 @@ architecture rtl of dionysos_top is reset_n_o => fpga_reset_n_ff_100 -- reset 100 clocks delayed ); + gen_led_g_o <= (others => '1'); + gen_led_r_o <= (others => '1'); + + gp_led_o <= (others => '1'); + -- NIOSII CPU flash_reset_n_o <= '1'; fash_acc_o <= '0'; -- Hardware Write Protect input (accelerated program operations) @@ -408,30 +415,31 @@ architecture rtl of dionysos_top is sdo_from_the_epcs_flash_controller_0 => config_asd0_o, -- TSE MAC - -- ena_10_from_the_triple_speed_ethernet_0 => ena_10_from_the_triple_speed_ethernet_0, - -- eth_mode_from_the_triple_speed_ethernet_0 => eth_mode_from_the_triple_speed_ethernet_0, - gm_rx_d_to_the_triple_speed_ethernet_0 => (others => '0'), - gm_rx_dv_to_the_triple_speed_ethernet_0 => '0', - gm_rx_err_to_the_triple_speed_ethernet_0 => '0', - -- gm_tx_d_from_the_triple_speed_ethernet_0 => gm_tx_d_from_the_triple_speed_ethernet_0, - -- gm_tx_en_from_the_triple_speed_ethernet_0 => gm_tx_en_from_the_triple_speed_ethernet_0, - -- gm_tx_err_from_the_triple_speed_ethernet_0 => gm_tx_err_from_the_triple_speed_ethernet_0, - m_rx_col_to_the_triple_speed_ethernet_0 => et_phy2_col_1_i, - m_rx_crs_to_the_triple_speed_ethernet_0 => '1', -- et_phy2_crs_1_i is not the same in rmii mode - m_rx_d_to_the_triple_speed_ethernet_0 => mii_rxd_to_mac_0, - m_rx_en_to_the_triple_speed_ethernet_0 => mii_rx_dv_to_mac_0, - m_rx_err_to_the_triple_speed_ethernet_0 => '0', - mdio_in_to_the_triple_speed_ethernet_0 => mac_mdio_in, - m_tx_d_from_the_triple_speed_ethernet_0 => mii_txd_from_mac_0, - m_tx_en_from_the_triple_speed_ethernet_0 => mii_tx_en_from_mac_0, - -- m_tx_err_from_the_triple_speed_ethernet_0 => m_tx_err_from_the_triple_speed_ethernet_0, - mdc_from_the_triple_speed_ethernet_0 => et_phy2_mdc_o, - mdio_oen_from_the_triple_speed_ethernet_0 => mac_mdio_en_n, - mdio_out_from_the_triple_speed_ethernet_0 => mac_mdio_out, - rx_clk_to_the_triple_speed_ethernet_0 => pll_clk_25, - set_1000_to_the_triple_speed_ethernet_0 => '0', -- tie to 0 if not used - set_10_to_the_triple_speed_ethernet_0 => '0', -- tie to 0 if not used - tx_clk_to_the_triple_speed_ethernet_0 => pll_clk_25 + -- ena_10_from_the_tse_mac => ena_10_from_the_tse_mac, + -- eth_mode_from_the_tse_mac => eth_mode_from_the_tse_mac, + gm_rx_d_to_the_tse_mac => (others => '0'), + gm_rx_dv_to_the_tse_mac => '0', + gm_rx_err_to_the_tse_mac => '0', + -- gm_tx_d_from_the_tse_mac => gm_tx_d_from_the_tse_mac, + -- gm_tx_en_from_the_tse_mac => gm_tx_en_from_the_tse_mac, + -- gm_tx_err_from_the_tse_mac => gm_tx_err_from_the_tse_mac, + m_rx_col_to_the_tse_mac => et_phy2_col_1_i, + m_rx_crs_to_the_tse_mac => '1', -- et_phy2_crs_1_i is not the same in rmii mode + m_rx_d_to_the_tse_mac => mii_rxd_to_mac_0, + m_rx_en_to_the_tse_mac => mii_rx_dv_to_mac_0, + m_rx_err_to_the_tse_mac => '0', + + m_tx_d_from_the_tse_mac => mii_txd_from_mac_0, + m_tx_en_from_the_tse_mac => mii_tx_en_from_mac_0, + -- m_tx_err_from_the_tse_mac => m_tx_err_from_the_tse_mac, + mdio_in_to_the_tse_mac => mac_mdio_in, + mdc_from_the_tse_mac => et_phy2_mdc_o, + mdio_oen_from_the_tse_mac => mac_mdio_en_n, + mdio_out_from_the_tse_mac => mac_mdio_out, + rx_clk_to_the_tse_mac => pll_clk_25, + set_1000_to_the_tse_mac => '0', -- tie to 0 if not used + set_10_to_the_tse_mac => '0', -- tie to 0 if not used + tx_clk_to_the_tse_mac => pll_clk_25 ); --------------------------------------------------------------------- @@ -459,8 +467,8 @@ architecture rtl of dionysos_top is reset_n_i => reset_n, clk_25_i => pll_clk_25, clk_50_i => pll_clk_50, - rmii_crs_i => et_phy2_crs_1_i, - + rmii_link_i => '1', -- et_phy2_crs_1_i is not the same in RMII mode + -- Transmit Path mii_tx_en_i => mii_tx_en_from_mac_0, mii_txd_i => mii_txd_from_mac_0, @@ -472,7 +480,7 @@ architecture rtl of dionysos_top is rmii_rxd_i => et_phy2_rxd_1_i(1 downto 0), mii_rx_dv_o => mii_rx_dv_to_mac_0, - mii_rxd_o => mii_rxd_to_mac_0 + mii_rxd_o => mii_rxd_to_mac_0 ); et_phy2_txd_2_o(3 downto 2) <= "00"; @@ -482,8 +490,8 @@ architecture rtl of dionysos_top is reset_n_i => reset_n, clk_25_i => pll_clk_25, clk_50_i => pll_clk_50, - rmii_crs_i => et_phy2_crs_2_i, - + rmii_link_i => '1', -- et_phy2_crs_2_i is not the same in RMII mode + -- Transmit Path mii_tx_en_i => mii_tx_en_from_mac_1, mii_txd_i => mii_txd_from_mac_1, @@ -495,7 +503,7 @@ architecture rtl of dionysos_top is rmii_rxd_i => et_phy2_rxd_2_i(1 downto 0), mii_rx_dv_o => mii_rx_dv_to_mac_1, - mii_rxd_o => mii_rxd_to_mac_1 + mii_rxd_o => mii_rxd_to_mac_1 ); ------------------------------------------------------------------------ -- cgit v1.2.3-54-g00ecf