From be1f6f5f6a204e4279699b7a427c1f1c45ea338b Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 26 Mar 2010 16:21:03 +0100 Subject: Rename project, correctly instantiate SOPC system --- dionysos_top.vhd | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'dionysos_top.vhd') diff --git a/dionysos_top.vhd b/dionysos_top.vhd index faa6b65..208b967 100644 --- a/dionysos_top.vhd +++ b/dionysos_top.vhd @@ -16,7 +16,7 @@ ------------|----------|----------------------------------------- -- 14.02.07 | kelt |file created for SInet ------------|----------|----------------------------------------- --- 22.02.10 | klto |file adjusted for dionysos-nios2mmu project +-- 22.02.10 | klto |file adjusted for dionysos_nios2mmu project ----------------------------------------------------------------- library ieee; @@ -198,12 +198,12 @@ architecture rtl of dionysos_top is --! \li EPCS Controller --! \n See \subpage nios_config_page for details - cpu : entity work.cpu_0 + dionysos_nios2mmu_inst : work.dionysos_nios2mmu port map( - clk => pll_clk_50, + clk_0 => pll_clk_50, reset_n => reset_nios_n, - -- the_sdram_0 + -- sdram_0 zs_addr_from_the_sdram_0 => dram_a_o(11 downto 0), -- dram_a_o(12) is for 32Mbit SDRAM zs_ba_from_the_sdram_0 => dram_ba, zs_cas_n_from_the_sdram_0 => dram_cas_n_o, @@ -214,22 +214,22 @@ architecture rtl of dionysos_top is zs_ras_n_from_the_sdram_0 => dram_ras_n_o, zs_we_n_from_the_sdram_0 => dram_we_n_o, - -- the_tri_state_bridge_0_avalon_slave + -- tri_state_bridge_0 select_n_to_the_cfi_flash_0 => flash_ce_n_o, tri_state_bridge_0_address => flash_a_o, tri_state_bridge_0_data => flash_d_io, tri_state_bridge_0_readn => flash_oe_n_o, write_n_to_the_cfi_flash_0 => flash_we_n_o, - -- the_uart_0 + -- uart_0 rxd_to_the_uart_0 => nios_uart_rxd_i, txd_from_the_uart_0 => nios_uart_txd_o, - -- the_epcs_controller - data0_to_the_epcs_controller => config_data0_i, - dclk_from_the_epcs_controller => config_dclk_o, - sce_from_the_epcs_controller => config_ce_n_o, - sdo_from_the_epcs_controller => config_asd0_o + -- epcs_controller + data0_to_the_epcs_flash_controller_0 => config_data0_i, + dclk_from_the_epcs_flash_controller_0 => config_dclk_o, + sce_from_the_epcs_flash_controller_0 => config_ce_n_o, + sdo_from_the_epcs_flash_controller_0 => config_asd0_o ); --@} end rtl; -- cgit v1.2.3-54-g00ecf