From a61a0a0cb72ad6b1fe1816a886fe5aa23c8b1442 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 12 Aug 2011 10:39:40 +0200 Subject: Add ISP1362 component --- lib/bus/avalon/ISP1362_CTRL.v | 60 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 lib/bus/avalon/ISP1362_CTRL.v (limited to 'lib/bus/avalon/ISP1362_CTRL.v') diff --git a/lib/bus/avalon/ISP1362_CTRL.v b/lib/bus/avalon/ISP1362_CTRL.v new file mode 100644 index 0000000..56f8020 --- /dev/null +++ b/lib/bus/avalon/ISP1362_CTRL.v @@ -0,0 +1,60 @@ +module ISP1362_CTRL (//Avalon Interface + clk, address, readdata, writedata, writedata_avalon_slave_1, chipselect_n, read_n, write_n, reset_n, write_n_avalon_slave_1, irq_n, irq_n_avalon_slave_1, + //Phillips USB controller + OTG_ADDR, OTG_DATA, OTG_CS_N, OTG_RD_N, OTG_WR_N, OTG_RST_N, OTG_INT0, OTG_INT1, OTG_FSPEED, OTG_LSPEED, OTG_DACK0_N, OTG_DACK1_N); + + //Avalon Interface + input clk, chipselect_n, read_n, write_n, reset_n, write_n_avalon_slave_1; + input [1:0] address; + input [15:0] writedata; + input [7:0] writedata_avalon_slave_1; + output [15:0] readdata; + output irq_n, irq_n_avalon_slave_1; + + //Phillips USB controller + output [1:0] OTG_ADDR; + inout [15:0] OTG_DATA; + output OTG_CS_N, OTG_RD_N, OTG_WR_N, OTG_RST_N; + input OTG_INT0, OTG_INT1; + output OTG_FSPEED, OTG_LSPEED, OTG_DACK0_N, OTG_DACK1_N; + + //Registers + reg [15:0] data, readdata; + reg [1:0] OTG_ADDR; + reg OTG_CS_N, OTG_RD_N, OTG_WR_N; + reg irq_n, irq_n_avalon_slave_1; + + //Assignments + assign OTG_RST_N = reset_n; + assign OTG_DATA = OTG_WR_N ? 16'hZZZZ : data; + assign OTG_DACK0_N = 1'b1, OTG_DACK1_N = 1'b1; + assign OTG_FSPEED = 0, OTG_LSPEED = 0; + + //Reset condition + always @ (posedge clk or negedge reset_n) + begin + if (reset_n==0) + begin + data <= 0; + readdata <= 0; + OTG_ADDR <= 0; + OTG_CS_N <= 1; + OTG_RD_N <= 1; + OTG_WR_N <= 1; + irq_n <= 1; + irq_n_avalon_slave_1 <= 1; + end + + else + begin + data <= writedata; + readdata <= OTG_DATA; + OTG_ADDR <= address; + OTG_CS_N <= chipselect_n; + OTG_RD_N <= read_n; + OTG_WR_N <= write_n; + irq_n <= OTG_INT0; + irq_n_avalon_slave_1 <= OTG_INT1; + end + end +endmodule -- cgit v1.2.3-54-g00ecf