------------------------------------------------------------------ -- _____ ______ _____ - -- |_ _| | ____|/ ____| Institute of Embedded Systems - -- | | _ __ | |__ | (___ Zuercher Hochschule fuer - -- | | | '_ \| __| \___ \ angewandte Wissenschaften - -- _| |_| | | | |____ ____) | (University of Applied Sciences) - -- |_____|_| |_|______|_____/ 8401 Winterthur, Switzerland - ------------------------------------------------------------------ -- -- $LastChangedDate: $ -- $Rev: $ -- $Author: $ ----------------------------------------------------------------- -- -- Change History -- Date |Name |Modification ------------|----------|----------------------------------------- -- 14.02.07 | kelt |file created for SInet ------------|----------|----------------------------------------- -- 22.02.10 | klto |file adjusted for dionysos_nios2mmu project ----------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library ines_misc; use ines_misc.reset_sync_pkg.all; use ines_misc.bibuf_async_pkg.all; library ines_ethernet; use ines_ethernet.rmii_in_out_pkg.all; use ines_ethernet.mdio_interface_pkg.all; --! \brief Top file for design on Dionysos board entity dionysos_top is port( --!@name Clock and reset inputs --@{ clock_50_i : in std_logic; --! 50 MHz system clock fpga_reset_n_i : in std_logic; --! FPGA reset from voltage monitor --@} --!@name Cyclone EPCS config device interface --@{ --! \anchor epcs_grp config_ce_n_o : out std_logic; --! Cyclone EPCS config device chip select config_asd0_o : out std_logic; --! Cyclone EPCS config device address config_data0_i : in std_logic; --! Cyclone EPCS config device data config_dclk_o : out std_logic; --! Cyclone EPCS config device clock --@} --!@name RS232 for Linux console --@{ --! \anchor rs_linux_grp nios_uart_rxd_i : in std_logic; --! Linux console UART Receiver nios_uart_txd_o : out std_logic; --! Linux console UART Transmitter --@} --!@name GP-LEDs --@{ --! \anchor led_grp gp_led_o : out std_logic_vector(3 downto 0); --! general purpose LEDs gen_led_g_o : out std_logic_vector(6 downto 0); --! green LEDs at front cover gen_led_r_o : out std_logic_vector(6 downto 0); --! red LEDs at front cover --@} --!@name DPDT Switch --@{ --! \anchor switch_grp switch_i : in std_logic_vector(3 downto 0); --! Dip-Switch[3:0] --@} --!@name Reserve Pins --@{ reserve0_i : in std_logic; --! unused pin reserve1_i : in std_logic; --! unused pin reserve2_i : in std_logic; --! unused pin reserve3_i : in std_logic; --! unused pin reserve4_i : in std_logic; --! unused pin reserve5_i : in std_logic; --! unused pin reserve6_i : in std_logic; --! unused pin reserve7_i : in std_logic; --! unused pin reserve8_i : in std_logic; --! unused pin --@} --!@name SDRAM Interface --@{ --! \anchor sdram_grp dram_d_io : inout std_logic_vector(15 downto 0); --! SDRAM Data bus 16 Bits dram_a_o : out std_logic_vector(12 downto 0); --! SDRAM Address bus 12 Bits dram_clk_o : out std_logic; --! SDRAM Clock dram_cke_o : out std_logic; --! SDRAM Clock Enable dram_ldqm_o : out std_logic; --! SDRAM Low-byte Data Mask dram_udqm_o : out std_logic; --! SDRAM High-byte Data Mask dram_we_n_o : out std_logic; --! SDRAM Write Enable dram_cas_n_o : out std_logic; --! SDRAM Column Address Strobe dram_ras_n_o : out std_logic; --! SDRAM Row Address Strobe dram_cs_n_o : out std_logic; --! SDRAM Chip Select dram_ba0_n_o : out std_logic; --! SDRAM Bank Address 0 dram_ba1_n_o : out std_logic; --! SDRAM Bank Address 0 --@} --!@name ISP1362 Interface --@{ --! \anchor isp1362_grp otg_d_io : inout std_logic_vector(15 downto 0); --! ISP1362 Data bus 16 Bits otg_a_o : out std_logic_vector(1 downto 0); --! ISP1362 Address 2 Bits otg_cs_n_o : out std_logic; --! ISP1362 Chip Select otg_oe_n_o : out std_logic; --! ISP1362 Write otg_we_n_o : out std_logic; --! ISP1362 Read otg_reset_n_o : out std_logic; --! ISP1362 Reset otg_int0_i : in std_logic; --! ISP1362 Interrupt 0 otg_int1_i : in std_logic; --! ISP1362 Interrupt 1 otg_dreq0_i : in std_logic; --! ISP1362 DMA Request 0 otg_dreq1_i : in std_logic; --! ISP1362 DMA Request 1 otg_dack0_n_o : out std_logic; --! ISP1362 DMA Acknowledge 0 otg_dack1_n_o : out std_logic; --! ISP1362 DMA Acknowledge 1 usb_clk_i : in std_logic; --! 12MHz USB clock --@} --!@name Flash Interface --@{ --! \anchor flash_grp flash_d_io : inout std_logic_vector(7 downto 0); --! FLASH Data bus 8 Bits flash_a_o : out std_logic_vector(21 downto 0); --! FLASH Address bus 22 Bits flash_we_n_o : out std_logic; --! FLASH Write Enable flash_reset_n_o : out std_logic; --! FLASH Reset flash_oe_n_o : out std_logic; --! FLASH Output Enable flash_ce_n_o : out std_logic; --! FLASH Chip Enable fash_acc_o : out std_logic; --! --@} --!@name 100BaseTX Phy0 & Phy1 50 MHz Clock output --@{ --! \anchor phy11_grp et_phy_clk_50mhz_o : out std_logic; --! PHY clock for all RMII ethernet phys et_phy1_tx_clk_1_i : in std_logic; --! PHY clock in MII mode (not used in RMII mode) et_phy1_rx_clk_1_i : in std_logic; --! PHY clock in MII mode (not used in RMII mode) et_phy2_rx_clk_2_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) et_phy2_tx_clk_2_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) et_phy2_rx_clk_1_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) et_phy2_tx_clk_1_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) et_phy1_rx_clk_2_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) et_phy1_tx_clk_2_i : in std_logic; --! PHY2 clock in MII mode (not used in RMII mode) --@} --!@name 100BaseTX Phy1 Port 1 --@{ --! \anchor phy11_grp et_phy1_rxd_1_i : in std_logic_vector(3 downto 0); --! Dual eth phy1: phy1 receive data et_phy1_rx_dv_1_i : in std_logic; --! Dual eth phy1: phy1 rx data valid et_phy1_crs_1_i : in std_logic; --! Dual eth phy1: phy1 carrier sense et_phy1_col_1_i : in std_logic; --! Dual eth phy1: phy1 collision detect et_phy1_txd_1_o : out std_logic_vector(3 downto 0); --! Dual eth phy1: phy1 transmit data et_phy1_tx_en_1_o : out std_logic; --! Dual eth phy1: phy1 tx enable et_phy1_int_1_i : in std_logic; --! Dual eth phy1: phy1 interrupt/power down (not used) et_phy1_rx_er_1_i : in std_logic; --! Dual eth phy1: phy1 error (not used) --@} --!@name 100BaseTX Phy1 Port 2 --@{ --! \anchor phy12_grp et_phy1_rxd_2_i : in std_logic_vector(3 downto 0); --! Dual eth phy1: phy2 receive data et_phy1_rx_dv_2_i : in std_logic; --! Dual eth phy1: phy2 rx data valid et_phy1_crs_2_i : in std_logic; --! Dual eth phy1: phy2 carrier sense et_phy1_col_2_i : in std_logic; --! Dual eth phy1: phy2 collision detect et_phy1_txd_2_o : out std_logic_vector(3 downto 0); --! Dual eth phy1: phy2 transmit data et_phy1_tx_en_2_o : out std_logic; --! Dual eth phy1: phy2 tx enable et_phy1_int_2_i : in std_logic; --! Dual eth phy1: phy2 interrupt/power down (not used) et_phy1_rx_er_2_i : in std_logic; --! Dual eth phy1: phy2 error (not used) --@} --!@name 100BaseTX Phy2 Port 1 --@{ --! \anchor phy11_grp et_phy2_rxd_1_i : in std_logic_vector(3 downto 0); --! Dual eth phy1: phy1 receive data et_phy2_rx_dv_1_i : in std_logic; --! Dual eth phy1: phy1 rx data valid et_phy2_crs_1_i : in std_logic; --! Dual eth phy1: phy1 carrier sense et_phy2_col_1_i : in std_logic; --! Dual eth phy1: phy1 collision detect et_phy2_txd_1_o : out std_logic_vector(3 downto 0); --! Dual eth phy1: phy1 transmit data et_phy2_tx_en_1_o : out std_logic; --! Dual eth phy1: phy1 tx enable et_phy2_int_1_i : in std_logic; --! Dual eth phy1: phy1 interrupt/power down (not used) et_phy2_rx_er_1_i : in std_logic; --! Dual eth phy1: phy1 error (not used) --@} --!@name 100BaseTX Phy2 Port 2 --@{ --! \anchor phy12_grp et_phy2_rxd_2_i : in std_logic_vector(3 downto 0); --! Dual eth phy1: phy2 receive data et_phy2_rx_dv_2_i : in std_logic; --! Dual eth phy1: phy2 rx data valid et_phy2_crs_2_i : in std_logic; --! Dual eth phy1: phy2 carrier sense et_phy2_col_2_i : in std_logic; --! Dual eth phy1: phy2 collision detect et_phy2_txd_2_o : out std_logic_vector(3 downto 0); --! Dual eth phy1: phy2 transmit data et_phy2_tx_en_2_o : out std_logic; --! Dual eth phy1: phy2 tx enable et_phy2_int_2_i : in std_logic; --! Dual eth phy1: phy2 interrupt/power down (not used) et_phy2_rx_er_2_i : in std_logic; --! Dual eth phy1: phy2 error (not used) --@} --!@name Phy 1 configuration (MDIO, reset) --@{ --! \anchor mdio_grp et_phy1_mdc_o : out std_logic; --! Dual eth phy1, phy2 Management clock et_phy1_mdio_io : inout std_logic; --! Dual eth phy1, phy2 data rst_et_phy1_n_o : out std_logic; --! Ethernet phy reset --@} --!@name Phy 2 configuration (MDIO, reset) --@{ --! \anchor mdio_grp et_phy2_mdc_o : out std_logic; --! Dual eth phy1, phy2 Management clock et_phy2_mdio_io : inout std_logic; --! Dual eth phy1, phy2 data rst_et_phy2_n_o : out std_logic --! Ethernet phy reset --@} ); end dionysos_top; architecture rtl of dionysos_top is --! FPGA main clock frequency (50MHz) constant C_FPGA_FREQ : integer := 50000000; --! front pannel LEDs signal leds : std_logic_vector(15 downto 0); --! @name SDRAM Data --@{ --! Nios SDRAM controller data mask (byte select) signal dram_dqm : std_logic_vector(1 downto 0); --! Nios SDRAM controller bank address signal dram_ba : std_logic_vector(1 downto 0); --@} --! 50 MHz Clock which is Source Synchronous to the DRAM Data signal pll_clk_50 : std_logic; --! 25 MHz Clock signal pll_clk_25 : std_logic; --! 12.5 MHz Clock signal pll_clk_12_5 : std_logic; --! main design reset after reset circuit signal reset_n : std_logic; --! synchronous reset signal fpga_reset_n_ff : std_logic; --! synchronous reset signal fpga_reset_n_ff_100 : std_logic; --! Reset for the NIOS. Active in Ethernet Modus (no DSL) signal reset_nios_n : std_logic; --@} --! @name RX byte stream interface of ethernet phy 1 --! (see \subpage bs_interface_stb) --@{ --! Ethernet phy 1 RMII receive data signal et_phy1_rx_data_1 : std_logic_vector(7 downto 0); signal et_phy1_rx_data_2 : std_logic_vector(7 downto 0); --! Ethernet phy 1 RMII receive strobe signal et_phy1_rx_stb_1 : std_logic; signal et_phy1_rx_stb_2 : std_logic; --! Ethernet phy 1 RMII receive data valid signal et_phy1_rx_dv_1 : std_logic; signal et_phy1_rx_dv_2 : std_logic; --@} --! \page bs_interface_stb Bytestream Interface (Strobe) --! \image html timingdiagramme_bytestream_interface_stb.png "bytestream interface with strobe signal" --! @name RX interface 2 of ethernet phy 2 --@{ --! Ethernet phy 2 port 2 RMII receive data signal et_phy2_rx_data_2 : std_logic_vector(7 downto 0); --! Ethernet phy 2 port 2 RMII receive strobe signal et_phy2_rx_stb_2 : std_logic; --! Ethernet phy 2 port 2 RMII receive data valid signal et_phy2_rx_dv_2 : std_logic; --@} --! @name TX interface 2 of ethernet phy 2 --@{ --! Ethernet phy 2 port 2 RMII transmit data signal et_phy2_txd_2 : std_logic_vector(7 downto 0); --! Ethernet phy 2 port 2 RMII transmit eanble signal et_phy2_tx_en_2 : std_logic; --! Ethernet phy 2 port 2 RMII transmit data acknowledge signal et_phy2_tx_ack_2 : std_logic; --@} --! link status of ethernet interfaces (from MDIO) signal et_phy1_link_status : std_logic_vector(3 downto 0); --! synchronised on clock dip switch states signal sw_sync : std_logic_vector(switch_i'range); --! @name MDIO signals (100BaseTX phy configuration interface) --@{ --! output enable for mdio data signal et_phy1_mdio_oe : std_logic; signal et_phy2_mdio_oe : std_logic; --! mdio data input signal et_phy1_mdio_in : std_logic; signal et_phy2_mdio_in : std_logic; --! mdio data output signal et_phy1_mdio_out : std_logic; signal et_phy2_mdio_out : std_logic; --@} --! @name Signals between TSE mac (MII mode) and RMII bridge --@{ signal mii_txd_from_mac_0 : std_logic_vector(3 downto 0); signal mii_rx_dv_to_mac_0 : std_logic; signal mii_rxd_to_mac_0 : std_logic_vector(3 downto 0); signal mii_tx_en_from_mac_0 : std_logic; signal mii_txd_from_mac_1 : std_logic_vector(3 downto 0); signal mii_rx_dv_to_mac_1 : std_logic; signal mii_rxd_to_mac_1 : std_logic_vector(3 downto 0); signal mii_tx_en_from_mac_1 : std_logic; signal mac_mdio_in : std_logic; signal mac_mdio_out : std_logic; signal mac_mdio_en : std_logic; signal mac_mdio_en_n : std_logic; --@} begin --! @name Components --@{ -- generate ETH-PHY 50MHz clock --! PLL to generate all clocks dram clock (shift -3ns) sinet_pll : entity work.sinet_pll port map ( inclk0 => clock_50_i, -- 50 MHz in c0 => pll_clk_50, -- 50MHz source synchronous clock out c1 => pll_clk_25, -- 25MHz clock output c2 => pll_clk_12_5, -- 12.5MHz clock output c3 => dram_clk_o -- 50MHz clock output (-3ns) ); -- generate ETH-PHY 50MHz clock et_phy_clk_50mhz_o <= pll_clk_50; --! synchronize reset reset_n_sync : reset_sync generic map( STAGES => 2 ) port map( clk_i => pll_clk_50, reset1_n_i => fpga_reset_n_i, reset2_n_i => '1', reset_n_o => fpga_reset_n_ff ); rst_et_phy1_n_o <= fpga_reset_n_ff; -- reset for de RMII-PHY 0 rst_et_phy2_n_o <= fpga_reset_n_ff_100; -- reset for de RMII-PHY 1 --! Delay reset => Latch in Time from Power up for the RMII-Phy (min 167ms) reset_gen : reset_sync generic map( STAGES => 10000000 --200ms ) port map( clk_i => pll_clk_50, reset1_n_i => fpga_reset_n_ff, reset2_n_i => '1', reset_n_o => reset_n -- reset for all other components ); --! Delay reset for PHY Nr. 2 => so that the two phy's aren't exactly synchron reset_gen_100 : reset_sync generic map( STAGES => 100 --2us ) port map( clk_i => pll_clk_50, reset1_n_i => fpga_reset_n_ff, reset2_n_i => '1', reset_n_o => fpga_reset_n_ff_100 -- reset 100 clocks delayed ); gen_led_g_o <= (others => '1'); gen_led_r_o <= (others => '1'); gp_led_o <= (others => '1'); -- NIOSII CPU flash_reset_n_o <= '1'; fash_acc_o <= '0'; -- Hardware Write Protect input (accelerated program operations) dram_ldqm_o <= dram_dqm(0); dram_udqm_o <= dram_dqm(1); dram_ba0_n_o <= dram_ba(0); dram_ba1_n_o <= dram_ba(1); reset_nios_n <= reset_n; --! \brief Altera SOPC-Builder component --! \details --! \li NiosII CPU --! \li SDRAM Interface --! \li Flash Interface --! \li Uart --! \li EPCS Controller --! \n See \subpage nios_config_page for details dionysos_nios2mmu_inst : work.dionysos_nios2mmu port map( clk_0 => pll_clk_50, reset_n => reset_nios_n, -- sdram_0 zs_addr_from_the_sdram_0 => dram_a_o(12 downto 0), -- 64MB -- zs_addr_from_the_sdram_0 => dram_a_o(11 downto 0), -- 16MB zs_ba_from_the_sdram_0 => dram_ba, zs_cas_n_from_the_sdram_0 => dram_cas_n_o, zs_cke_from_the_sdram_0 => dram_cke_o, zs_cs_n_from_the_sdram_0 => dram_cs_n_o, zs_dq_to_and_from_the_sdram_0 => dram_d_io, zs_dqm_from_the_sdram_0 => dram_dqm, zs_ras_n_from_the_sdram_0 => dram_ras_n_o, zs_we_n_from_the_sdram_0 => dram_we_n_o, -- tri_state_bridge_0 select_n_to_the_cfi_flash_0 => flash_ce_n_o, tri_state_bridge_0_address => flash_a_o, tri_state_bridge_0_data => flash_d_io, tri_state_bridge_0_readn => flash_oe_n_o, write_n_to_the_cfi_flash_0 => flash_we_n_o, -- uart_0 rxd_to_the_uart_0 => nios_uart_rxd_i, txd_from_the_uart_0 => nios_uart_txd_o, -- epcs_controller data0_to_the_epcs_flash_controller_0 => config_data0_i, dclk_from_the_epcs_flash_controller_0 => config_dclk_o, sce_from_the_epcs_flash_controller_0 => config_ce_n_o, sdo_from_the_epcs_flash_controller_0 => config_asd0_o, -- TSE MAC -- ena_10_from_the_tse_mac => ena_10_from_the_tse_mac, -- eth_mode_from_the_tse_mac => eth_mode_from_the_tse_mac, gm_rx_d_to_the_tse_mac => (others => '0'), gm_rx_dv_to_the_tse_mac => '0', gm_rx_err_to_the_tse_mac => '0', -- gm_tx_d_from_the_tse_mac => gm_tx_d_from_the_tse_mac, -- gm_tx_en_from_the_tse_mac => gm_tx_en_from_the_tse_mac, -- gm_tx_err_from_the_tse_mac => gm_tx_err_from_the_tse_mac, m_rx_col_to_the_tse_mac => et_phy2_col_1_i, m_rx_crs_to_the_tse_mac => '1', -- et_phy2_crs_1_i is not the same in rmii mode m_rx_d_to_the_tse_mac => mii_rxd_to_mac_0, m_rx_en_to_the_tse_mac => mii_rx_dv_to_mac_0, m_rx_err_to_the_tse_mac => '0', m_tx_d_from_the_tse_mac => mii_txd_from_mac_0, m_tx_en_from_the_tse_mac => mii_tx_en_from_mac_0, -- m_tx_err_from_the_tse_mac => m_tx_err_from_the_tse_mac, mdio_in_to_the_tse_mac => mac_mdio_in, mdc_from_the_tse_mac => et_phy2_mdc_o, mdio_oen_from_the_tse_mac => mac_mdio_en_n, mdio_out_from_the_tse_mac => mac_mdio_out, rx_clk_to_the_tse_mac => pll_clk_25, set_1000_to_the_tse_mac => '0', -- tie to 0 if not used set_10_to_the_tse_mac => '0', -- tie to 0 if not used tx_clk_to_the_tse_mac => pll_clk_25, -- ISP1362 USB OTG controller OTG_ADDR_from_the_ISP1362 => otg_a_o, OTG_CS_N_from_the_ISP1362 => otg_cs_n_o, OTG_DACK0_N_from_the_ISP1362 => otg_dack0_n_o, OTG_DACK1_N_from_the_ISP1362 => otg_dack1_n_o, OTG_DATA_to_and_from_the_ISP1362 => otg_d_io, OTG_FSPEED_from_the_ISP1362 => open, OTG_LSPEED_from_the_ISP1362 => open, OTG_RD_N_from_the_ISP1362 => otg_oe_n_o, OTG_RST_N_from_the_ISP1362 => otg_reset_n_o, OTG_WR_N_from_the_ISP1362 => otg_we_n_o, OTG_INT0_to_the_ISP1362 => otg_int0_i, OTG_INT1_to_the_ISP1362 => otg_int1_i ); --------------------------------------------------------------------- -- ethernet MDIO for connection between TSE and PHY 2 --------------------------------------------------------------------- --! MDIO bidirectional data buffer mdio_phy_2_data_buf : bibuf_async port map( oe => mac_mdio_en, io => et_phy2_mdio_io, inp => mac_mdio_out, outp => mac_mdio_in ); mac_mdio_en <= not mac_mdio_en_n; ------------------------------------------------------------------------ -- Converts the rmii interface to the mii interface ------------------------------------------------------------------------ et_phy2_txd_1_o(3 downto 2) <= "00"; rmii_phy_to_mii_mac_0 : entity ines_ethernet.rmii_phy_to_mii_mac port map( reset_n_i => reset_n, clk_25_i => pll_clk_25, clk_50_i => pll_clk_50, rmii_link_i => '1', -- et_phy2_crs_1_i is not the same in RMII mode -- Transmit Path mii_tx_en_i => mii_tx_en_from_mac_0, mii_txd_i => mii_txd_from_mac_0, rmii_tx_en_o => et_phy2_tx_en_1_o, rmii_txd_o => et_phy2_txd_1_o(1 downto 0), -- Receive Path rmii_rx_dv_i => et_phy2_rx_dv_1_i, rmii_rxd_i => et_phy2_rxd_1_i(1 downto 0), mii_rx_dv_o => mii_rx_dv_to_mac_0, mii_rxd_o => mii_rxd_to_mac_0 ); et_phy2_txd_2_o(3 downto 2) <= "00"; rmii_phy_to_mii_mac_1 : entity ines_ethernet.rmii_phy_to_mii_mac port map( reset_n_i => reset_n, clk_25_i => pll_clk_25, clk_50_i => pll_clk_50, rmii_link_i => '1', -- et_phy2_crs_2_i is not the same in RMII mode -- Transmit Path mii_tx_en_i => mii_tx_en_from_mac_1, mii_txd_i => mii_txd_from_mac_1, rmii_tx_en_o => et_phy2_tx_en_2_o, rmii_txd_o => et_phy2_txd_2_o(1 downto 0), -- Receive Path rmii_rx_dv_i => et_phy2_rx_dv_2_i, rmii_rxd_i => et_phy2_rxd_2_i(1 downto 0), mii_rx_dv_o => mii_rx_dv_to_mac_1, mii_rxd_o => mii_rxd_to_mac_1 ); ------------------------------------------------------------------------ -- MDIO Interface ------------------------------------------------------------------------ --! MDIO interface for ethernet phy configuration mdio : entity ines_ethernet.mdio_interface generic map( C_SET_TO_MII => false, CLK_DIVIDER => 10, -- divider for MDC CHK_INTERVAL => 50e6, -- link check interval in clk_i cycles -- CHK_INTERVAL => 500, -- for Testbench NO_OF_PORTS => 2, -- number of ports to poll => max 4 ADDR_PORT_1 => 0, ADDR_PORT_2 => 1, ADDR_PORT_3 => 2, ADDR_PORT_4 => 3) port map( clk_i => pll_clk_50, reset_n_i => reset_n, -- manual access (could be connected to the CPU interface...) phy_addr_i => (others => '0'), phy_reg_i => (others => '0'), phy_data_i => (others => '0'), phy_data_o => open, send_i => '0', read_i => '0', busy_n_o => open, -- Status out link_o => et_phy1_link_status, -- 1= link OK reset_phy_i => (others => '0'), -- 1= reset phy -- MDIO mdio_i => et_phy1_mdio_in, mdio_o => et_phy1_mdio_out, mdio_oe_o => et_phy1_mdio_oe, mdc_o => et_phy1_mdc_o ); --! MDIO bidirectional data buffer mdio_data_buf : bibuf_async port map( oe => et_phy1_mdio_oe, io => et_phy1_mdio_io, inp => et_phy1_mdio_out, outp => et_phy1_mdio_in ); --@} end rtl;