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/*
* This devicetree is generated by sopc2dts on Fri Nov 02 10:51:22 CET 2012
* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
*/
/dts-v1/;
/ {
model = "ALTR,dionysos_nios2mmu";
compatible = "ALTR,dionysos_nios2mmu";
#address-cells = < 1 >;
#size-cells = < 1 >;
cpus {
#address-cells = < 1 >;
#size-cells = < 0 >;
cpu_0: cpu@0x0 {
device_type = "cpu";
compatible = "ALTR,nios2-9.1";
reg = < 0x00000000 >;
interrupt-controller;
#interrupt-cells = < 1 >;
clock-frequency = < 50000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */
dcache-line-size = < 32 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */
icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */
dcache-size = < 2048 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */
icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */
ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/
ALTR,pid-num-bits = < 14 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */
ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */
ALTR,tlb-num-entries = < 256 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */
ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */
ALTR,has-div; /* embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT type NUMBER*/
ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/
ALTR,reset-addr = < 0xc4000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */
ALTR,fast-tlb-miss-addr = < 0xc4802000 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */
ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */
}; //end cpu@0x0 (cpu_0)
}; //end cpus
memory@0 {
device_type = "memory";
reg = < 0x00000000 0x04000000
0x04802000 0x00000800 >;
}; //end memory@0
sopc@0 {
device_type = "soc";
ranges;
#address-cells = < 1 >;
#size-cells = < 1 >;
compatible = "ALTR,avalon", "simple-bus";
bus-frequency = < 50000000 >;
epcs_flash_controller_0: spi@0x5000400 {
compatible = "ALTR,spi-9.1", "ALTR,spi-1.0";
reg = < 0x05000400 0x00000800 >;
interrupt-parent = < &cpu_0 >;
interrupts = < 1 >;
bank-width = < 2 >;
device-width = < 1 >;
#address-cells = < 1 >;
#size-cells = < 0 >;
m25p80@0 {
compatible = "m25p80";
spi-max-frequency = < 25000000 >;
reg = < 0 >;
}; //end m25p80@0
}; //end spi@0x5000400 (epcs_flash_controller_0)
cfi_flash_0: flash@0x4000000 {
compatible = "ALTR,cfi_flash-9.1", "cfi-flash";
reg = < 0x04000000 0x00400000 >;
bank-width = < 1 >;
device-width = < 1 >;
}; //end flash@0x4000000 (cfi_flash_0)
timer_0: timer@0x4400000 {
compatible = "ALTR,timer-9.1", "ALTR,timer-1.0";
reg = < 0x04400000 0x00000020 >;
interrupt-parent = < &cpu_0 >;
interrupts = < 0 >;
clock-frequency = < 50000000 >;
}; //end timer@0x4400000 (timer_0)
uart_0: serial@0x6000000 {
compatible = "ALTR,uart-9.1", "ALTR,uart-1.0";
reg = < 0x06000000 0x00000020 >;
interrupt-parent = < &cpu_0 >;
interrupts = < 2 >;
current-speed = < 115200 >; /* embeddedsw.CMacro.BAUD type NUMBER */
clock-frequency = < 50000000 >; /* embeddedsw.CMacro.FREQ type NUMBER */
}; //end serial@0x6000000 (uart_0)
jtag_uart_0: serial@0x7000000 {
compatible = "ALTR,juart-9.1", "ALTR,juart-1.0";
reg = < 0x07000000 0x00000008 >;
interrupt-parent = < &cpu_0 >;
interrupts = < 3 >;
}; //end serial@0x7000000 (jtag_uart_0)
tse_mac: ethernet@0x8002400 {
compatible = "ALTR,tse-9.1", "ALTR,tse-1.0";
reg = < 0x08002400 0x00000400
0x08100000 0x00000040
0x08200000 0x00000040
0x04840000 0x00002000 >;
interrupt-parent = < &cpu_0 >;
interrupts = < 4 5 >;
ALTR,rx-fifo-depth = < 1024 >; /* embeddedsw.CMacro.RECEIVE_FIFO_DEPTH type NUMBER */
ALTR,tx-fifo-depth = < 1024 >; /* embeddedsw.CMacro.TRANSMIT_FIFO_DEPTH type NUMBER */
address-bits = < 48 >;
max-frame-size = < 1518 >;
local-mac-address = [ 00 00 00 00 00 00 ];
phy-mode = "gmii";
ALTR,mii-id = < 0 >;
}; //end ethernet@0x8002400 (tse_mac)
watchdog_timer: watchdog@0x4880000 {
compatible = "ALTR,wdt-9.1", "ALTR,wdt-1.0";
reg = < 0x04880000 0x00000020 >;
interrupt-parent = < &cpu_0 >;
interrupts = < 6 >;
clock-frequency = < 50000000 >;
timeout = < 249999999 >; /* embeddedsw.CMacro.LOAD_VALUE type NUMBER */
}; //end watchdog@0x4880000 (watchdog_timer)
sysid: sysid@0x8000000 {
compatible = "ALTR,sysid-9.1", "ALTR,sysid-1.0";
reg = < 0x08000000 0x00000008 >;
}; //end sysid@0x8000000 (sysid)
ISP1362: isp1362@0x8220000 {
compatible = "nxp,isp1362-1.0", "nxp,usb-isp1362";
reg = < 0x08220000 0x00000004
0x08220004 0x00000004
0x08220020 0x00000004
0x08220024 0x00000004 >;
interrupt-parent = < &cpu_0 >;
interrupts = < 8 7 >;
}; //end isp1362@0x8220000 (ISP1362)
pio_leds_front: gpio@0x4400020 {
compatible = "ALTR,pio-9.1", "ALTR,pio-1.0";
reg = < 0x04400020 0x00000020 >;
width = < 16 >; /* width type NUMBER */
resetvalue = < 0 >; /* resetValue type NUMBER */
#gpio-cells = < 2 >;
gpio-controller;
}; //end gpio@0x4400020 (pio_leds_front)
pio_leds_board: gpio@0x4400040 {
compatible = "ALTR,pio-9.1", "ALTR,pio-1.0";
reg = < 0x04400040 0x00000020 >;
width = < 4 >; /* width type NUMBER */
resetvalue = < 0 >; /* resetValue type NUMBER */
#gpio-cells = < 2 >;
gpio-controller;
}; //end gpio@0x4400040 (pio_leds_board)
pio_dipswitch: gpio@0x4400060 {
compatible = "ALTR,pio-9.1", "ALTR,pio-1.0";
reg = < 0x04400060 0x00000010 >;
interrupt-parent = < &cpu_0 >;
interrupts = < 9 >;
width = < 4 >; /* width type NUMBER */
resetvalue = < 0 >; /* resetValue type NUMBER */
#gpio-cells = < 2 >;
gpio-controller;
}; //end gpio@0x4400060 (pio_dipswitch)
leds {
compatible = "gpio-leds";
heartbeat {
label = "heartbeat";
gpios = <&pio_leds_front 6 0>;
linux,default-trigger = "heartbeat";
};
blinky {
label = "blinky";
gpios = <&pio_leds_front 5 0>;
linux,default-trigger = "timer";
};
blinky2 {
label = "blinky2";
gpios = <&pio_leds_board 0 0>;
linux,default-trigger = "timer";
};
};
}; //end sopc@0
chosen {
bootargs = "debug console=ttyAL0,115200";
}; //end chosen
}; //end /
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