summaryrefslogtreecommitdiff
path: root/dionysos_top.vhd
blob: faa6b654a484a34c6bf98f7e199f3e64216bf65d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
------------------------------------------------------------------
--  _____       ______  _____                                    -
-- |_   _|     |  ____|/ ____|  Institute of Embedded Systems    -
--   | |  _ __ | |__  | (___    Zuercher Hochschule fuer         -
--   | | | '_ \|  __|  \___ \   angewandte Wissenschaften        -
--  _| |_| | | | |____ ____) |  (University of Applied Sciences) -
-- |_____|_| |_|______|_____/   8401 Winterthur, Switzerland     -
------------------------------------------------------------------
-- $LastChangedDate: 2008-02-06 14:28:53 +0100 (Mi, 06 Feb 2008) $
-- $Rev: 828 $
-- $Author: ffar $
-----------------------------------------------------------------
--
-- Change History
-- Date     |Name      |Modification
------------|----------|-----------------------------------------
-- 14.02.07 | kelt     |file created for SInet
------------|----------|-----------------------------------------
-- 22.02.10 | klto     |file adjusted for dionysos-nios2mmu project
-----------------------------------------------------------------

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
library ines_misc;
  use ines_misc.reset_sync_pkg.all;

--! \brief Top file for design on Dionysos board
entity dionysos_top is
  port(
    --!@name Clock and reset inputs
    --@{
    clock_50_i            : in  std_logic;                        --!  50 MHz system clock
    fpga_reset_n_i        : in  std_logic;                        --!  FPGA reset from voltage monitor
    --@}

    --!@name Cyclone EPCS config device interface
    --@{
    --! \anchor epcs_grp
    config_ce_n_o         : out std_logic;                        --! Cyclone EPCS config device chip select
    config_asd0_o         : out std_logic;                        --! Cyclone EPCS config device address
    config_data0_i        : in  std_logic;                        --! Cyclone EPCS config device data
    config_dclk_o         : out std_logic;                        --! Cyclone EPCS config device clock
    --@}

    --!@name  RS232 for Linux console
    --@{
    --! \anchor rs_linux_grp
    nios_uart_rxd_i       : in  std_logic;                        --! Linux console UART Receiver
    nios_uart_txd_o       : out std_logic;                        --! Linux console UART Transmitter
    --@}

    --!@name GP-LEDs
    --@{
    --! \anchor led_grp
    gp_led_o              : out std_logic_vector(3 downto 0);     --! general purpose LEDs
    gen_led_g_o           : out std_logic_vector(6 downto 0);     --! green LEDs at front cover
    gen_led_r_o           : out std_logic_vector(6 downto 0);     --! red LEDs at front cover
    --@}

    --!@name DPDT Switch
    --@{
    --! \anchor switch_grp
    switch_i              : in  std_logic_vector(3 downto 0);     --! Dip-Switch[3:0]
    --@}

    --!@name Reserve Pins
    --@{
    reserve0_i            : in  std_logic;                        --! unused pin
    reserve1_i            : in  std_logic;                        --! unused pin
    reserve2_i            : in  std_logic;                        --! unused pin
    reserve3_i            : in  std_logic;                        --! unused pin
    reserve4_i            : in  std_logic;                        --! unused pin
    reserve5_i            : in  std_logic;                        --! unused pin
    reserve6_i            : in  std_logic;                        --! unused pin
    reserve7_i            : in  std_logic;                        --! unused pin
    reserve8_i            : in  std_logic;                        --! unused pin
    --@}

    --!@name SDRAM Interface
    --@{
    --! \anchor sdram_grp
    dram_d_io             : inout std_logic_vector(15 downto 0);  --! SDRAM Data bus 16 Bits
    dram_a_o              : out std_logic_vector(12 downto 0);    --! SDRAM Address bus 12 Bits
    dram_clk_o            : out std_logic;                        --! SDRAM Clock
    dram_cke_o            : out std_logic;                        --! SDRAM Clock Enable
    dram_ldqm_o           : out std_logic;                        --! SDRAM Low-byte Data Mask
    dram_udqm_o           : out std_logic;                        --! SDRAM High-byte Data Mask
    dram_we_n_o           : out std_logic;                        --! SDRAM Write Enable
    dram_cas_n_o          : out std_logic;                        --! SDRAM Column Address Strobe
    dram_ras_n_o          : out std_logic;                        --! SDRAM Row Address Strobe
    dram_cs_n_o           : out std_logic;                        --! SDRAM Chip Select
    dram_ba0_n_o          : out std_logic;                        --! SDRAM Bank Address 0
    dram_ba1_n_o          : out std_logic;                        --! SDRAM Bank Address 0
    --@}

    --!@name Flash Interface
    --@{
    --! \anchor flash_grp
    flash_d_io            : inout std_logic_vector(7 downto 0);   --! FLASH Data bus 8 Bits
    flash_a_o             : out std_logic_vector(21 downto 0);    --! FLASH Address bus 22 Bits
    flash_we_n_o          : out std_logic;                        --! FLASH Write Enable
    flash_reset_n_o       : out std_logic;                        --! FLASH Reset
    flash_oe_n_o          : out std_logic;                        --! FLASH Output Enable
    flash_ce_n_o          : out std_logic;                        --! FLASH Chip Enable
    fash_acc_o            : out std_logic                         --!
    --@}
  );
end dionysos_top;

architecture rtl of dionysos_top is

  --! FPGA main clock frequency (50MHz)
  constant C_FPGA_FREQ            : integer := 50000000;

  --! 50 MHz Clock which is Source Synchronous to the DRAM Data
  signal pll_clk_50               : std_logic;
  --! 25 MHz Clock
  signal pll_clk_25               : std_logic;
  --! 12.5 MHz Clock
  signal pll_clk_12_5                 : std_logic;
  --! main design reset after reset circuit
  signal reset_n                  : std_logic;
  --! synchronous reset
  signal fpga_reset_n_ff          : std_logic;
  --! Reset for the NIOS. Active in Ethernet Modus (no DSL)
  signal reset_nios_n             : std_logic;

  --! front pannel LEDs
  signal leds                     : std_logic_vector(15 downto 0);

  --! @name SDRAM Data
  --@{
  --! Nios SDRAM controller data mask (byte select)
  signal dram_dqm                 : std_logic_vector(1 downto 0);
  --! Nios SDRAM controller bank address
  signal dram_ba                  : std_logic_vector(1 downto 0);
  --@}

  --! synchronised on clock dip switch states
  signal sw_sync                 : std_logic_vector(switch_i'range);

  begin
--! @name Components
--@{

  -- generate ETH-PHY 50MHz clock

  --! PLL to generate all clocks dram clock (shift -3ns)
  sinet_pll : entity work.sinet_pll
  port map (
    inclk0 => clock_50_i,    -- 50 MHz in
    c0     => pll_clk_50,    -- 50MHz source synchronous clock out
    c1     => pll_clk_25,    -- 25MHz clock output
    c2     => pll_clk_12_5,  -- 12.5MHz clock output
    c3     => dram_clk_o     -- 50MHz clock output (-3ns)
  );

  --! synchronize reset
  reset_n_sync : reset_sync
  generic map(
    STAGES     => 2
  )
  port map(
    clk_i      => pll_clk_50,
    reset1_n_i => fpga_reset_n_i,
    reset2_n_i => '1',
    reset_n_o  => fpga_reset_n_ff
  );

  --! Delay reset => Latch in Time from Power up for the RMII-Phy (min 167ms)
  reset_gen : reset_sync
  generic map(
    STAGES     => 10000000 --200ms
  )
  port map(
    clk_i      => pll_clk_50,
    reset1_n_i => fpga_reset_n_ff,
    reset2_n_i => '1',
    reset_n_o  => reset_n             -- reset for all other components
  );

  -- NIOSII CPU
  flash_reset_n_o  <= '1';
  fash_acc_o       <= '0'; -- Hardware Write Protect input (accelerated program operations)
  dram_ldqm_o      <= dram_dqm(0);
  dram_udqm_o      <= dram_dqm(1);
  dram_ba0_n_o     <= dram_ba(0);
  dram_ba1_n_o     <= dram_ba(1);
  reset_nios_n     <= reset_n;

  --! \brief Altera SOPC-Builder component
  --! \details
  --! \li NiosII CPU
  --! \li SDRAM Interface
  --! \li Flash Interface
  --! \li Uart
  --! \li EPCS Controller
  --! \n See \subpage nios_config_page for details

  cpu : entity work.cpu_0
    port map(
      clk                                         => pll_clk_50,
      reset_n                                     => reset_nios_n,

      -- the_sdram_0
      zs_addr_from_the_sdram_0                    => dram_a_o(11 downto 0), -- dram_a_o(12) is for 32Mbit SDRAM
      zs_ba_from_the_sdram_0                      => dram_ba,
      zs_cas_n_from_the_sdram_0                   => dram_cas_n_o,
      zs_cke_from_the_sdram_0                     => dram_cke_o,
      zs_cs_n_from_the_sdram_0                    => dram_cs_n_o,
      zs_dq_to_and_from_the_sdram_0               => dram_d_io,
      zs_dqm_from_the_sdram_0                     => dram_dqm,
      zs_ras_n_from_the_sdram_0                   => dram_ras_n_o,
      zs_we_n_from_the_sdram_0                    => dram_we_n_o,

      -- the_tri_state_bridge_0_avalon_slave
      select_n_to_the_cfi_flash_0                 => flash_ce_n_o,
      tri_state_bridge_0_address                  => flash_a_o,
      tri_state_bridge_0_data                     => flash_d_io,
      tri_state_bridge_0_readn                    => flash_oe_n_o,
      write_n_to_the_cfi_flash_0                  => flash_we_n_o,

      -- the_uart_0
      rxd_to_the_uart_0                           => nios_uart_rxd_i,
      txd_from_the_uart_0                         => nios_uart_txd_o,

      -- the_epcs_controller
      data0_to_the_epcs_controller                => config_data0_i,
      dclk_from_the_epcs_controller               => config_dclk_o,
      sce_from_the_epcs_controller                => config_ce_n_o,
      sdo_from_the_epcs_controller                => config_asd0_o
    );
--@}
end rtl;