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| author | Thierry Reding <treding@nvidia.com> | 2015-08-03 13:20:49 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-07-04 11:35:46 +0200 |
| commit | 33a8eb8d40ee7fc07f23a407607bdbaa46893b2d (patch) | |
| tree | 1a329f79c826febc5af299ef645801f85fb3a914 /Documentation | |
| parent | 2ccb396e9dd4536cfb7e8c4fd892d215c7aec2b6 (diff) | |
drm/tegra: dc: Implement runtime PM
Use runtime PM to clock-gate, assert reset and powergate the display
controller. This ties in nicely with atomic DPMS in that a runtime PM
reference is taken before a pipe is enabled and dropped after it has
been shut down.
To make sure this works, make sure to only ever update planes on active
CRTCs, otherwise register accesses to a clock-gated and reset CRTC will
hang the CPU.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions