summaryrefslogtreecommitdiff
path: root/Documentation
diff options
context:
space:
mode:
authorMarc Zyngier <marc.zyngier@arm.com>2016-05-25 15:26:36 +0100
committerChristoffer Dall <christoffer.dall@linaro.org>2016-05-31 16:12:16 +0200
commit637d122baac7ff386c8e96df38ac88cee1551db9 (patch)
tree3877decc283a8c351c2c6d55621cf56ee5d6f2ea /Documentation
parentdf7942d17e1623d7358fe895377293637de5521b (diff)
KVM: arm/arm64: vgic-v3: Always resample level interrupts
When reading back from the list registers, we need to perform two actions for level interrupts: 1) clear the soft-pending bit if the interrupt is not pending anymore *in the list register* 2) resample the line level and propagate it to the pending state But these two actions shouldn't be linked, and we should *always* resample the line level, no matter what state is in the list register. Otherwise, we may end-up injecting spurious interrupts that have been already retired. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions