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| author | Yakir Yang <ykk@rock-chips.com> | 2016-06-29 17:15:05 +0800 |
|---|---|---|
| committer | Yakir Yang <ykk@rock-chips.com> | 2016-07-05 09:16:38 +0800 |
| commit | cb5571fcf809860c455f6b62bb5252f277b52e83 (patch) | |
| tree | ce79819098ac319e19fceb05c5d6db9484221e20 /Documentation | |
| parent | d9c900b0270a18101403cf5e95c1639fccd43a9f (diff) | |
drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1
There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special
registers setting").
The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions