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authorChen-Yu Tsai <wens@csie.org>2016-07-26 15:04:23 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-08-08 19:27:33 +0200
commit156ad0d7eae4825a0d94a4bf68571e97302f2501 (patch)
tree0df7832c241ef24add6cb62d8f59ac77a72ad18e /Documentation
parentfbe359f12ce40e3126bea959b135656e4a305897 (diff)
clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock
The condition passed to read*_poll_timeout() is the break condition, i.e. wait for this condition to happen and return success. The original code assumed the opposite, resulting in a warning when the PLL clock rate was changed but never lost it's lock as far as the readout indicated. This was verified by checking the read out register value. Fixes: 1d80c14248d6 ("clk: sunxi-ng: Add common infrastructure") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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