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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2017-02-06 13:05:16 +1100
committerMichael Ellerman <mpe@ellerman.id.au>2017-02-09 14:54:33 +1100
commit90c1e3c2fafec57fcb55b5d69bcf293b1a5fc8b3 (patch)
treeea2bf611c6112a0fe03d1277ab62cbfc51cded92 /arch/arm/boot
parentd7df2443cd5f67fc6ee7c05a88e4996e8177f91b (diff)
powerpc/mm/radix: Update ERAT flushes when invalidating TLB
Three tiny changes to the ERAT flushing logic: First don't make it depend on DD1. It hasn't been decided yet but we might run DD2 in a mode that also requires explicit flushes for performance reasons so make it unconditional. We also add a missing isync, and finally remove the flush from _tlbiel_va as it is only necessary for congruence-class invalidations (PID, LPID and full TLB), not targetted invalidations. Fixes: 96ed1fe511a8 ("powerpc/mm/radix: Invalidate ERAT on tlbiel for POWER9 DD1") Cc: stable@vger.kernel.org # v4.9+ Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/arm/boot')
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