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authorVivek Gautam <vivek.gautam@codeaurora.org>2017-01-04 16:18:09 +0000
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-01-04 18:22:47 +0100
commit01d0d2c42a14cee8f619d3e9d571ce3469f5ef51 (patch)
tree3d0e97d8e9686e4a453983312c5cdc73d4753847 /include/soc
parente09ee853c92011860a4bd2fbdf6126f60fc16bd3 (diff)
nvmem: qfprom: Allow single byte accesses for read/write
The nvmem core driver supports to read and write single byte. So, allow qfprom to support this feature. This change helps in extracting a required value based on bit-offset and number of bits for the required value in the nvmem cell. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/soc')
0 files changed, 0 insertions, 0 deletions
artially reverted. - the remaining four patches are to Intel embedded SoCs: baytrail (three patches) and merrifield (one patch): register access debounce fixes and a missing spinlock" * tag 'pinctrl-v4.10-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler pinctrl: baytrail: Debounce register is one per community pinctrl: baytrail: Rectify debounce support (part 2) pinctrl: intel: merrifield: Add missed check in mrfld_config_set() pinctrl: sunxi: Don't enforce bias disable (for now) pinctrl: berlin-bg4ct: fix the value for "sd1a" of pin SCRD0_CRD_PRES
Diffstat (limited to 'drivers/usb/gadget/udc/Makefile')