diff options
| author | Christoffer Dall <christoffer.dall@linaro.org> | 2016-12-10 21:13:51 +0100 |
|---|---|---|
| committer | Sudeep Holla <sudeep.holla@arm.com> | 2016-12-30 14:54:30 +0000 |
| commit | 368400e242dc04963ca5ff0b70654f1470344a0a (patch) | |
| tree | 3fb888e43b9cd8b94333ab1d4d3d1526e09a6d30 /include/soc | |
| parent | 7ce7d89f48834cefece7804d38fc5d85382edf77 (diff) | |
ARM: dts: vexpress: Support GICC_DIR operations
The GICv2 CPU interface registers span across 8K, not 4K as indicated in
the DT. Only the GICC_DIR register is located after the initial 4K
boundary, leaving a functional system but without support for separately
EOI'ing and deactivating interrupts.
After this change the system supports split priority drop and interrupt
deactivation.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
[sudeep.holla@arm.com: included same fix for tc1 platform too]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Diffstat (limited to 'include/soc')
0 files changed, 0 insertions, 0 deletions