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authorDaniel Jurgens <danielj@mellanox.com>2015-11-19 17:12:26 +0200
committerSaeed Mahameed <saeedm@mellanox.com>2017-02-06 18:17:25 +0200
commitf32f5bd2eb7e91a5090c06bbe1ed14bffbbda5d3 (patch)
tree297e2374d3fff18fb0296597fa58399af3278953 /net/802/Makefile
parenta61d5ce9cc56e2e41bbb1ad62ca7a16d7e7567bd (diff)
net/mlx5: Configure cache line size for start and end padding
There is a hardware feature that will pad the start or end of a DMA to be cache line aligned to avoid RMWs on the last cache line. The default cache line size setting for this feature is 64B. This change configures the hardware to use 128B alignment on systems with 128B cache lines. In addition we lower bound MPWRQ stride by HCA cacheline in mlx5e, MPWRQ stride should be at least the HCA cacheline, the current default is 64B and in case HCA_CAP.cach_line_128byte capability is set, MPWRQ RX stride will automatically be aligned to 128B. Signed-off-by: Daniel Jurgens <danielj@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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