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authorMarc Kleine-Budde <mkl@pengutronix.de>2015-09-01 08:57:55 +0200
committerMarc Kleine-Budde <mkl@pengutronix.de>2017-02-06 15:13:42 +0100
commit9eb7aa891101a4a09114ff3191f9877ea35eae06 (patch)
tree33826e4957f696a23f55d007d71a44490082b5bd /net/irda/irlan/Makefile
parent4bd888a80b1d48dbd83f1cbf806e923a30051958 (diff)
can: flexcan: add quirk FLEXCAN_QUIRK_ENABLE_EACEN_RRS
In order to receive RTR frames in the non HW FIFO mode the RSS and EACEN bits of the reg_ctrl2 have to be activated. As this has no side effect in the FIFO mode, we do this unconditionally on cores with the reg_ctrl2. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'net/irda/irlan/Makefile')
0 files changed, 0 insertions, 0 deletions
om `pl330_alloc_chan_resources', so the lock is already held. Function `pl330_release_channel' is called from `pl330_free_chan_resources', which already holds the lock, and from `pl330_del'. Function `pl330_del' is called in an error path of `pl330_probe' and at the end of `pl330_remove', but I assume that there cannot be concurrent accesses to the protected data at those points. Signed-off-by: Iago Abal <mail@iagoabal.eu> Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'include/net/sctp')