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generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-01-31 11:59:18 +0000
a5de5b74a50113564a1e0850e2da96c37c35e55d (diff)
ASoC: tlv320aic3x: Mark the RESET register as volatile
The RESET register only have one self clearing bit and it should not be cached. If it is cached, when we sync the registers back to the chip we will initiate a software reset as well, which is not desirable. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/trace/events/tlb.h')