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generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-05-09 16:48:36 +0000
t-next.git/commit/drivers/clk/rockchip/clk.h?id=9387bfd19b457085189d918ef117ffd63c4d67a0'>9387bfd19b457085189d918ef117ffd63c4d67a0 (diff)
clk: rockchip: allow varying mux parameters for cpuclk pll-sources
Thers are only two parent PLLs that APLL and GPLL for core on the previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed GPLL as alternate parent when core is switching freq. Since RK3399 big.LITTLE architecture, we need to select and adapt more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')