diff options
| author | Chris Zhong <zyw@rock-chips.com> | 2016-07-18 22:34:34 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-07-18 15:38:28 +0100 |
| commit | 46dd2e28a90e48fbf1b7e253933fa3b7242e9b1b (patch) | |
| tree | 4bf92522aeb261947955bd1b6ab2330132f9e1c5 | |
| parent | 359d9abdc208c662d8c9ff2966a7c6014124f715 (diff) | |
ASoC: rockchip: correct the spdif clk
The spdif mclk should be 128 times of sample rate, and there is a
internal divider, the real rate of spdif mclk is mclk / (div + 1).
Hence, the original driver always get the good frequency for
48000/96000/44100/192000. But for 32000, the mclk is incorrect,
it should be 32000*128, but get 48000*128. Do not use the internal
divider here, just set all mclk to 128 * sample rate directly.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>