Xilinx SuperSpeed DWC3 USB SoC controller Required properties: - compatible: Should contain "xlnx,zynqmp-dwc3" - clocks: A list of phandles for the clocks listed in clock-names - clock-names: Should contain the following: "bus_clk" Master/Core clock, have to be >= 125 MHz for SS operation and >= 60MHz for HS operation "ref_clk" Clock source to core during PHY power down Required child node: A child node must exist to represent the core DWC3 IP block. The name of the node is not important. The content of the node is defined in dwc3.txt. Example device node: usb@0 { #address-cells = <0x2>; #size-cells = <0x1>; status = "okay"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk" "ref_clk"; clocks = <&clk125>, <&clk125>; ranges; dwc3@fe200000 { compatible = "snps,dwc3"; reg = <0x0 0xfe200000 0x40000>; interrupts = <0x0 0x41 0x4>; dr_mode = "host"; }; }; 6eededd984ad409bff201f436a7'/> net-next plumbingsTobias Klauser
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authorCyril Bur <cyrilbur@gmail.com>2016-09-14 18:02:16 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2016-10-04 20:33:17 +1100
commit5d176f751ee3c6eededd984ad409bff201f436a7 (patch)
treec760a51812c2cfd6c27fccf9bd0f4d303e984509
parent172f7aaa75d0eaae167edde25c08aae9059e80fc (diff)
powerpc: tm: Enable transactional memory (TM) lazily for userspace
Currently the MSR TM bit is always set if the hardware is TM capable. This adds extra overhead as it means the TM SPRS (TFHAR, TEXASR and TFAIR) must be swapped for each process regardless of if they use TM. For processes that don't use TM the TM MSR bit can be turned off allowing the kernel to avoid the expensive swap of the TM registers. A TM unavailable exception will occur if a thread does use TM and the kernel will enable MSR_TM and leave it so for some time afterwards. Signed-off-by: Cyril Bur <cyrilbur@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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