DA8XX USB OHCI controller

Required properties:

 - compatible: Should be "ti,da830-ohci"
 - reg:        Should contain one register range i.e. start and length
 - interrupts: Description of the interrupt line
 - phys:       Phandle for the PHY device
 - phy-names:  Should be "usb-phy"

Optional properties:
 - vbus-supply: phandle of regulator that controls vbus power / over-current

Example:

ohci: usb@0225000 {
        compatible = "ti,da830-ohci";
        reg = <0x225000 0x1000>;
        interrupts = <59>;
        phys = <&usb_phy 1>;
        phy-names = "usb-phy";
        vbus-supply = <&reg_usb_ohci>;
};
ody>
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<tr><th>author</th><td>Daniel Jurgens &lt;danielj@mellanox.com&gt;</td><td class='right'>2015-11-19 17:12:26 +0200</td></tr>
<tr><th>committer</th><td>Saeed Mahameed &lt;saeedm@mellanox.com&gt;</td><td class='right'>2017-02-06 18:17:25 +0200</td></tr>
<tr><th>commit</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/?h=nds-private-remove&amp;id=f32f5bd2eb7e91a5090c06bbe1ed14bffbbda5d3'>f32f5bd2eb7e91a5090c06bbe1ed14bffbbda5d3</a> (<a href='/cgit.cgi/linux/net-next.git/patch/?id=f32f5bd2eb7e91a5090c06bbe1ed14bffbbda5d3'>patch</a>)</td></tr>
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<tr><th>parent</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/?h=nds-private-remove&amp;id=a61d5ce9cc56e2e41bbb1ad62ca7a16d7e7567bd'>a61d5ce9cc56e2e41bbb1ad62ca7a16d7e7567bd</a> (<a href='/cgit.cgi/linux/net-next.git/diff/?h=nds-private-remove&amp;id=f32f5bd2eb7e91a5090c06bbe1ed14bffbbda5d3&amp;id2=a61d5ce9cc56e2e41bbb1ad62ca7a16d7e7567bd'>diff</a>)</td></tr></table>
<div class='commit-subject'>net/mlx5: Configure cache line size for start and end padding</div><div class='commit-msg'>There is a hardware feature that will pad the start or end of a DMA to
be cache line aligned to avoid RMWs on the last cache line. The default
cache line size setting for this feature is 64B. This change configures
the hardware to use 128B alignment on systems with 128B cache lines.

In addition we lower bound MPWRQ stride by HCA cacheline in mlx5e,
MPWRQ stride should be at least the HCA cacheline, the current default
is 64B and in case HCA_CAP.cach_line_128byte capability is set, MPWRQ RX
stride will automatically be aligned to 128B.

Signed-off-by: Daniel Jurgens &lt;danielj@mellanox.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@mellanox.com&gt;
</div><div class='diffstat-header'><a href='/cgit.cgi/linux/net-next.git/diff/?h=nds-private-remove&amp;id=f32f5bd2eb7e91a5090c06bbe1ed14bffbbda5d3'>Diffstat</a></div><table summary='diffstat' class='diffstat'>