/* * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * */ #include #include #include #include #include "soctherm.h" #define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1 << 31) #define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30) #define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29) #define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28) #define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27) #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18) #define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9) #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18) #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9) #define TEGRA210_THRESH_GRAIN 500 #define TEGRA210_BPTT 9 static const struct tegra_tsensor_configuration tegra210_tsensor_config = { .tall = 16300, .tiddq_en = 1, .ten_count = 1, .tsample = 120, .tsample_ate = 480, }; static const struct tegra_tsensor_group tegra210_tsensor_group_cpu = { .id = TEGRA124_SOCTHERM_SENSOR_CPU, .name = "cpu", .sensor_temp_offset = SENSOR_TEMP1, .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK, .pdiv = 8, .pdiv_ate = 8, .pdiv_mask = SENSOR_PDIV_CPU_MASK, .pllx_hotspot_diff = 10, .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK, .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, .thermtrip_enable_mask = TEGRA210_THERMTRIP_CPU_EN_MASK, .thermtrip_threshold_mask = TEGRA210_THERMTRIP_CPU_THRESH_MASK, .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU, .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, }; static const struct tegra_tsensor_group tegra210_tsensor_group_gpu = { .id = TEGRA124_SOCTHERM_SENSOR_GPU, .name = "gpu", .sensor_temp_offset = SENSOR_TEMP1, .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK, .pdiv = 8, .pdiv_ate = 8, .pdiv_mask = SENSOR_PDIV_GPU_MASK, .pllx_hotspot_diff = 5, .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK, .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, .thermtrip_enable_mask = TEGRA210_THERMTRIP_GPU_EN_MASK, .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK, .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU, .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, }; static const struct tegra_tsensor_group tegra210_tsensor_group_pll = { .id = TEGRA124_SOCTHERM_SENSOR_PLLX, .name = "pll", .sensor_temp_offset = SENSOR_TEMP2, .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK, .pdiv = 8, .pdiv_ate = 8, .pdiv_mask = SENSOR_PDIV_PLLX_MASK, .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, .thermtrip_enable_mask = TEGRA210_THERMTRIP_TSENSE_EN_MASK, .thermtrip_threshold_mask = TEGRA210_THERMTRIP_TSENSE_THRESH_MASK, .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE, .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, }; static const struct tegra_tsensor_group tegra210_tsensor_group_mem = { .id = TEGRA124_SOCTHERM_SENSOR_MEM, .name = "mem", .sensor_temp_offset = SENSOR_TEMP2, .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK, .pdiv = 8, .pdiv_ate = 8, .pdiv_mask = SENSOR_PDIV_MEM_MASK, .pllx_hotspot_diff = 0, .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK, .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, .thermtrip_enable_mask = TEGRA210_THERMTRIP_MEM_EN_MASK, .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK, .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM, .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, }; static const struct tegra_tsensor_group *tegra210_tsensor_groups[] = { &tegra210_tsensor_group_cpu, &tegra210_tsensor_group_gpu, &tegra210_tsensor_group_pll, &tegra210_tsensor_group_mem, }; static const struct tegra_tsensor tegra210_tsensors[] = { { .name = "cpu0", .base = 0xc0, .config = &tegra210_tsensor_config, .calib_fuse_offset = 0x098, .fuse_corr_alpha = 1085000, .fuse_corr_beta = 3244200, .group = &tegra210_tsensor_group_cpu, }, { .name = "cpu1", .base = 0xe0, .config = &tegra210_tsensor_config, .calib_fuse_offset = 0x084, .fuse_corr_alpha = 1126200, .fuse_corr_beta = -67500, .group = &tegra210_tsensor_group_cpu, }, { .name = "cpu2", .base = 0x100, .config = &tegra210_tsensor_config, .calib_fuse_offset = 0x088, .fuse_corr_alpha = 1098400, .fuse_corr_beta = 2251100, .group = &tegra210_tsensor_group_cpu, }, { .name = "cpu3", .base = 0x120, .config = &tegra210_tsensor_config, .calib_fuse_offset = 0x12c, .fuse_corr_alpha = 1108000, .fuse_corr_beta = 602700, .group = &tegra210_tsensor_group_cpu, }, { .name = "mem0", .base = 0x140, .config = &tegra210_tsensor_config, .calib_fuse_offset = 0x158, .fuse_corr_alpha = 1069200, .fuse_corr_beta = 3549900, .group = &tegra210_tsensor_group_mem, }, { .name = "mem1", .base = 0x160, .config = &tegra210_tsensor_config, .calib_fuse_offset = 0x15c, .fuse_corr_alpha = 1173700, .fuse_corr_beta = -6263600, .group = &tegra210_tsensor_group_mem, }, { .name = "gpu", .base = 0x180, .config = &tegra210_tsensor_config, .calib_fuse_offset = 0x154, .fuse_corr_alpha = 1074300, .fuse_corr_beta = 2734900, .group = &tegra210_tsensor_group_gpu, }, { .name = "pllx", .base = 0x1a0, .config = &tegra210_tsensor_config, .calib_fuse_offset = 0x160, .fuse_corr_alpha = 1039700, .fuse_corr_beta = 6829100, .group = &tegra210_tsensor_group_pll, }, }; /* * Mask/shift bits in FUSE_TSENSOR_COMMON and * FUSE_TSENSOR_COMMON, which are described in * tegra_soctherm_fuse.c */ static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = { .fuse_base_cp_mask = 0x3ff << 11, .fuse_base_cp_shift = 11, .fuse_base_ft_mask = 0x7ff << 21, .fuse_base_ft_shift = 21, .fuse_shift_ft_mask = 0x1f << 6, .fuse_shift_ft_shift = 6, .fuse_spare_realignment = 0, }; const struct tegra_soctherm_soc tegra210_soctherm = { .tsensors = tegra210_tsensors, .num_tsensors = ARRAY_SIZE(tegra210_tsensors), .ttgs = tegra210_tsensor_groups, .num_ttgs = ARRAY_SIZE(tegra210_tsensor_groups), .tfuse = &tegra210_soctherm_fuse, .thresh_grain = TEGRA210_THRESH_GRAIN, .bptt = TEGRA210_BPTT, .use_ccroc = false, }; ================================================= BUG kmalloc-128 (Tainted: G U ): Object already free ----------------------------------------------------------------------------- Disabling lock debugging due to kernel taint INFO: Allocated in drm_atomic_helper_setup_commit+0x285/0x2f0 [drm_kms_helper] age=0 cpu=3 pid=1529 ___slab_alloc+0x308/0x3b0 __slab_alloc+0xd/0x20 kmem_cache_alloc_trace+0x92/0x1c0 drm_atomic_helper_setup_commit+0x285/0x2f0 [drm_kms_helper] intel_atomic_commit+0x35/0x4f0 [i915] drm_atomic_commit+0x46/0x50 [drm] drm_mode_atomic_ioctl+0x7d4/0xab0 [drm] drm_ioctl+0x2b3/0x490 [drm] do_vfs_ioctl+0x69c/0x700 SyS_ioctl+0x4e/0x80 entry_SYSCALL_64_fastpath+0x13/0x94 INFO: Freed in drm_event_cancel_free+0xa3/0xb0 [drm] age=0 cpu=3 pid=1529 __slab_free+0x48/0x2e0 kfree+0x159/0x1a0 drm_event_cancel_free+0xa3/0xb0 [drm] drm_mode_atomic_ioctl+0x86d/0xab0 [drm] drm_ioctl+0x2b3/0x490 [drm] do_vfs_ioctl+0x69c/0x700 SyS_ioctl+0x4e/0x80 entry_SYSCALL_64_fastpath+0x13/0x94 INFO: Slab 0xffffde1f0997b080 objects=17 used=2 fp=0xffff92fb65ec2578 flags=0x200000000008101 INFO: Object 0xffff92fb65ec2578 @offset=1400 fp=0xffff92fb65ec2ae8 Redzone ffff92fb65ec2570: bb bb bb bb bb bb bb bb ........ Object ffff92fb65ec2578: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec2588: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec2598: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec25a8: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec25b8: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec25c8: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec25d8: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk Object ffff92fb65ec25e8: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b a5 kkkkkkkkkkkkkkk. Redzone ffff92fb65ec25f8: bb bb bb bb bb bb bb bb ........ Padding ffff92fb65ec2738: 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZ CPU: 3 PID: 180 Comm: kworker/3:2 Tainted: G BU 4.10.0-rc6-patser+ #5039 Hardware name: /NUC5PPYB, BIOS PYBSWCEL.86A.0031.2015.0601.1712 06/01/2015 Workqueue: events intel_atomic_helper_free_state [i915] Call Trace: dump_stack+0x4d/0x6d print_trailer+0x20c/0x220 free_debug_processing+0x1c6/0x330 ? drm_atomic_state_default_clear+0xf7/0x1c0 [drm] __slab_free+0x48/0x2e0 ? drm_atomic_state_default_clear+0xf7/0x1c0 [drm] kfree+0x159/0x1a0 drm_atomic_state_default_clear+0xf7/0x1c0 [drm] ? drm_atomic_state_clear+0x30/0x30 [drm] intel_atomic_state_clear+0xd/0x20 [i915] drm_atomic_state_clear+0x1a/0x30 [drm] __drm_atomic_state_free+0x13/0x60 [drm] intel_atomic_helper_free_state+0x5d/0x70 [i915] process_one_work+0x260/0x4a0 worker_thread+0x2d1/0x4f0 kthread+0x127/0x130 ? process_one_work+0x4a0/0x4a0 ? kthread_stop+0x120/0x120 ret_from_fork+0x29/0x40 FIX kmalloc-128: Object at 0xffff92fb65ec2578 not freed Fixes: 3b24f7d67581 ("drm/atomic: Add struct drm_crtc_commit to track async updates") Fixes: 9626014258a5 ("drm/fence: add in-fences support") Cc: <stable@vger.kernel.org> # v4.8+ Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1485854725-27640-1-git-send-email-maarten.lankhorst@linux.intel.com
Diffstat (limited to 'sound/soc/blackfin/bf5xx-sport.c')