/* * Copyright (C) 2007 by Analog Devices, Inc. * * The Inventra Controller Driver for Linux is free software; you * can redistribute it and/or modify it under the terms of the GNU * General Public License version 2 as published by the Free Software * Foundation. */ #ifndef __MUSB_BLACKFIN_H__ #define __MUSB_BLACKFIN_H__ /* * Blackfin specific definitions */ /* Anomalies notes: * * 05000450 - USB DMA Mode 1 Short Packet Data Corruption: * MUSB driver is designed to transfer buffer of N * maxpacket size * in DMA mode 1 and leave the rest of the data to the next * transfer in DMA mode 0, so we never transmit a short packet in * DMA mode 1. * * 05000463 - This anomaly doesn't affect this driver since it * never uses L1 or L2 memory as data destination. * * 05000464 - This anomaly doesn't affect this driver since it * never uses L1 or L2 memory as data source. * * 05000465 - The anomaly can be seen when SCLK is over 100 MHz, and there is * no way to workaround for bulk endpoints. Since the wMaxPackSize * of bulk is less than or equal to 512, while the fifo size of * endpoint 5, 6, 7 is 1024, the double buffer mode is enabled * automatically when these endpoints are used for bulk OUT. * * 05000466 - This anomaly doesn't affect this driver since it never mixes * concurrent DMA and core accesses to the TX endpoint FIFOs. * * 05000467 - The workaround for this anomaly will introduce another * anomaly - 05000465. */ /* The Mentor USB DMA engine on BF52x (silicon v0.0 and v0.1) seems to be * unstable in host mode. This may be caused by Anomaly 05000380. After * digging out the root cause, we will change this number accordingly. * So, need to either use silicon v0.2+ or disable DMA mode in MUSB. */ #if ANOMALY_05000380 && defined(CONFIG_BF52x) && \ !defined(CONFIG_MUSB_PIO_ONLY) # error "Please use PIO mode in MUSB driver on bf52x chip v0.0 and v0.1" #endif #undef DUMP_FIFO_DATA #ifdef DUMP_FIFO_DATA static void dump_fifo_data(u8 *buf, u16 len) { u8 *tmp = buf; int i; for (i = 0; i < len; i++) { if (!(i % 16) && i) pr_debug("\n"); pr_debug("%02x ", *tmp++); } pr_debug("\n"); } #else #define dump_fifo_data(buf, len) do {} while (0) #endif #define USB_DMA_BASE USB_DMA_INTERRUPT #define USB_DMAx_CTRL 0x04 #define USB_DMAx_ADDR_LOW 0x08 #define USB_DMAx_ADDR_HIGH 0x0C #define USB_DMAx_COUNT_LOW 0x10 #define USB_DMAx_COUNT_HIGH 0x14 #define USB_DMA_REG(ep, reg) (USB_DMA_BASE + 0x20 * ep + reg) /* Almost 1 second */ #define TIMER_DELAY (1 * HZ) static struct timer_list musb_conn_timer; #endif /* __MUSB_BLACKFIN_H__ */ =''/>
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /sound/soc/amd
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'sound/soc/amd')