/* * Definitions for the KLSI KL5KUSB105 serial port adapter */ /* vendor/product pairs that are known to contain this chipset */ #define PALMCONNECT_VID 0x0830 #define PALMCONNECT_PID 0x0080 #define KLSI_VID 0x05e9 #define KLSI_KL5KUSB105D_PID 0x00c0 /* Vendor commands: */ /* port table -- the chip supports up to 4 channels */ /* baud rates */ enum { kl5kusb105a_sio_b115200 = 0, kl5kusb105a_sio_b57600 = 1, kl5kusb105a_sio_b38400 = 2, kl5kusb105a_sio_b19200 = 4, kl5kusb105a_sio_b14400 = 5, kl5kusb105a_sio_b9600 = 6, kl5kusb105a_sio_b4800 = 8, /* unchecked */ kl5kusb105a_sio_b2400 = 9, /* unchecked */ kl5kusb105a_sio_b1200 = 0xa, /* unchecked */ kl5kusb105a_sio_b600 = 0xb /* unchecked */ }; /* data bits */ #define kl5kusb105a_dtb_7 7 #define kl5kusb105a_dtb_8 8 /* requests: */ #define KL5KUSB105A_SIO_SET_DATA 1 #define KL5KUSB105A_SIO_POLL 2 #define KL5KUSB105A_SIO_CONFIGURE 3 /* values used for request KL5KUSB105A_SIO_CONFIGURE */ #define KL5KUSB105A_SIO_CONFIGURE_READ_ON 3 #define KL5KUSB105A_SIO_CONFIGURE_READ_OFF 2 /* Interpretation of modem status lines */ /* These need sorting out by individually connecting pins and checking * results. FIXME! * When data is being sent we see 0x30 in the lower byte; this must * contain DSR and CTS ... */ #define KL5KUSB105A_DSR ((1<<4) | (1<<5)) #define KL5KUSB105A_CTS ((1<<5) | (1<<4)) #define KL5KUSB105A_WANTS_TO_SEND 0x30 #if 0 #define KL5KUSB105A_DTR /* Data Terminal Ready */ #define KL5KUSB105A_CTS /* Clear To Send */ #define KL5KUSB105A_CD /* Carrier Detect */ #define KL5KUSB105A_DSR /* Data Set Ready */ #define KL5KUSB105A_RxD /* Receive pin */ #define KL5KUSB105A_LE #define KL5KUSB105A_RTS #define KL5KUSB105A_ST #define KL5KUSB105A_SR #define KL5KUSB105A_RI /* Ring Indicator */ #endif -next.git/commit/fs?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>commitdiff
path: root/fs
diff options
context:
space:
mode:
authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /fs
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'fs')