/***************************************************************************\ |* *| |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *| |* *| |* NOTICE TO USER: The source code is copyrighted under U.S. and *| |* international laws. Users and possessors of this source code are *| |* hereby granted a nonexclusive, royalty-free copyright license to *| |* use this code in individual and commercial software. *| |* *| |* Any use of this source code must include, in the user documenta- *| |* tion and internal comments to the code, notices to the end user *| |* as follows: *| |* *| |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| |* *| |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| |* *| |* U.S. Government End Users. This source code is a "commercial *| |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| |* consisting of "commercial computer software" and "commercial *| |* computer software documentation," as such terms are used in *| |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| |* ment only as a commercial end item. Consistent with 48 C.F.R. *| |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| |* all U.S. Government End Users acquire the source code with only *| |* those rights set forth herein. *| |* *| \***************************************************************************/ /* * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/ * XFree86 'nv' driver, this source code is provided under MIT-style licensing * where the source code is provided "as is" without warranty of any kind. * The only usage restriction is for the copyright notices to be retained * whenever code is used. * * Antonino Daplas 2005-03-11 */ #ifndef __NV_LOCAL_H__ #define __NV_LOCAL_H__ /* * This file includes any environment or machine specific values to access the * HW. Put all affected includes, typdefs, etc. here so the riva_hw.* files * can stay generic in nature. */ /* * HW access macros. These assume memory-mapped I/O, and not normal I/O space. */ #define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i))) #define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i))) #define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i))) #define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i))) #define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i))) #define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) /* VGA I/O is now always done through MMIO */ #define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i))) #define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i))) #define NVDmaNext(par, data) \ NV_WR32(&(par)->dmaBase[(par)->dmaCurrent++], 0, (data)) #define NVDmaStart(info, par, tag, size) { \ if((par)->dmaFree <= (size)) \ NVDmaWait(info, size); \ NVDmaNext(par, ((size) << 18) | (tag)); \ (par)->dmaFree -= ((size) + 1); \ } #if defined(__i386__) #define _NV_FENCE() outb(0, 0x3D0); #else #define _NV_FENCE() mb(); #endif #define WRITE_PUT(par, data) { \ _NV_FENCE() \ NV_RD08((par)->FbStart, 0); \ NV_WR32(&(par)->FIFO[0x0010], 0, (data) << 2); \ mb(); \ } #define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2) #ifdef __LITTLE_ENDIAN #include #define reverse_order(l) \ do { \ u8 *a = (u8 *)(l); \ a[0] = bitrev8(a[0]); \ a[1] = bitrev8(a[1]); \ a[2] = bitrev8(a[2]); \ a[3] = bitrev8(a[3]); \ } while(0) #else #define reverse_order(l) do { } while(0) #endif /* __LITTLE_ENDIAN */ #endif /* __NV_LOCAL_H__ */ href='/cgit.cgi/linux/net-next.git/tree/sound/soc/codecs/pcm1681.c?id=d7df2443cd5f67fc6ee7c05a88e4996e8177f91b'>sound/soc/codecs/pcm1681.c parenta0615a16f7d0ceb5804d295203c302d496d8ee91 (diff)
powerpc/mm: Fix spurrious segfaults on radix with autonuma
When autonuma (Automatic NUMA balancing) marks a PTE inaccessible it clears all the protection bits but leave the PTE valid. With the Radix MMU, an attempt at executing from such a PTE will take a fault with bit 35 of SRR1 set "SRR1_ISI_N_OR_G". It is thus incorrect to treat all such faults as errors. We should pass them to handle_mm_fault() for autonuma to deal with. The case of pages that are really not executable is handled by the existing test for VM_EXEC further down. That leaves us with catching the kernel attempts at executing user pages. We can catch that earlier, even before we do find_vma. It is never valid on powerpc for the kernel to take an exec fault to begin with. So fold that test with the existing test for the kernel faulting on kernel addresses to bail out early. Fixes: 1d18ad026844 ("powerpc/mm: Detect instruction fetch denied and report") Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Acked-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'sound/soc/codecs/pcm1681.c')