/*
 *  GOVR registers list for WM8505 chips
 *
 *  Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com>
 *   Based on VIA/WonderMedia wm8510-govrh-reg.h
 *   http://github.com/projectgus/kernel_wm8505/blob/wm8505_2.6.29/
 *         drivers/video/wmt/register/wm8510/wm8510-govrh-reg.h
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _WM8505FB_REGS_H
#define _WM8505FB_REGS_H

/*
 * Color space select register, default value 0x1c
 *   BIT0 GOVRH_DVO_YUV2RGB_ENABLE
 *   BIT1 GOVRH_VGA_YUV2RGB_ENABLE
 *   BIT2 GOVRH_RGB_MODE
 *   BIT3 GOVRH_DAC_CLKINV
 *   BIT4 GOVRH_BLANK_ZERO
 */
#define WMT_GOVR_COLORSPACE	0x1e4
/*
 * Another colorspace select register, default value 1
 *   BIT0 GOVRH_DVO_RGB
 *   BIT1 GOVRH_DVO_YUV422
 */
#define WMT_GOVR_COLORSPACE1	 0x30

#define WMT_GOVR_CONTRAST	0x1b8
#define WMT_GOVR_BRGHTNESS	0x1bc /* incompatible with RGB? */

/* Framubeffer address */
#define WMT_GOVR_FBADDR		 0x90
#define WMT_GOVR_FBADDR1	 0x94 /* UV offset in YUV mode */

/* Offset of visible window */
#define WMT_GOVR_XPAN		 0xa4
#define WMT_GOVR_YPAN		 0xa0

#define WMT_GOVR_XRES		 0x98
#define WMT_GOVR_XRES_VIRTUAL	 0x9c

#define WMT_GOVR_MIF_ENABLE	 0x80
#define WMT_GOVR_FHI		 0xa8
#define WMT_GOVR_REG_UPDATE	 0xe4

/*
 *   BIT0 GOVRH_DVO_OUTWIDTH
 *   BIT1 GOVRH_DVO_SYNC_POLAR
 *   BIT2 GOVRH_DVO_ENABLE
 */
#define WMT_GOVR_DVO_SET	0x148

/* Timing generator? */
#define WMT_GOVR_TG		0x100

/* Timings */
#define WMT_GOVR_TIMING_H_ALL	0x108
#define WMT_GOVR_TIMING_V_ALL	0x10c
#define WMT_GOVR_TIMING_V_START	0x110
#define WMT_GOVR_TIMING_V_END	0x114
#define WMT_GOVR_TIMING_H_START	0x118
#define WMT_GOVR_TIMING_H_END	0x11c
#define WMT_GOVR_TIMING_V_SYNC	0x128
#define WMT_GOVR_TIMING_H_SYNC	0x12c

#endif /* _WM8505FB_REGS_H */
</td><td class='form'><form class='right' method='get' action='/cgit.cgi/linux/net-next.git/log/include/drm/drm_agpsupport.h'>
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<div class='path'>path: <a href='/cgit.cgi/linux/net-next.git/commit/?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>root</a>/<a href='/cgit.cgi/linux/net-next.git/commit/include?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>include</a>/<a href='/cgit.cgi/linux/net-next.git/commit/include/drm?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>drm</a>/<a href='/cgit.cgi/linux/net-next.git/commit/include/drm/drm_agpsupport.h?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>drm_agpsupport.h</a></div><div class='content'><div class='cgit-panel'><b>diff options</b><form method='get'><input type='hidden' name='id' value='6e978b22efa1db9f6e71b24440b5f1d93e968ee3'/><table><tr><td colspan='2'/></tr><tr><td class='label'>context:</td><td class='ctrl'><select name='context' onchange='this.form.submit();'><option value='1'>1</option><option value='2'>2</option><option value='3' selected='selected'>3</option><option value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><table summary='commit info' class='commit-info'>
<tr><th>author</th><td>Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;</td><td class='right'>2017-02-03 14:18:39 -0800</td></tr>
<tr><th>committer</th><td>Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;</td><td class='right'>2017-02-04 00:11:08 +0100</td></tr>
<tr><th>commit</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/include/drm/drm_agpsupport.h?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>6e978b22efa1db9f6e71b24440b5f1d93e968ee3</a> (<a href='/cgit.cgi/linux/net-next.git/patch/include/drm/drm_agpsupport.h?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>patch</a>)</td></tr>
<tr><th>tree</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/tree/?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>c666f7a26b860674848949e39a610222b0723f89</a> /<a href='/cgit.cgi/linux/net-next.git/tree/include/drm/drm_agpsupport.h?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>include/drm/drm_agpsupport.h</a></td></tr>
<tr><th>parent</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/include/drm/drm_agpsupport.h?id=3c223c19aea85d3dda1416c187915f4a30b04b1f'>3c223c19aea85d3dda1416c187915f4a30b04b1f</a> (<a href='/cgit.cgi/linux/net-next.git/diff/include/drm/drm_agpsupport.h?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3&amp;id2=3c223c19aea85d3dda1416c187915f4a30b04b1f'>diff</a>)</td></tr></table>
<div class='commit-subject'>cpufreq: intel_pstate: Disable energy efficiency optimization</div><div class='commit-msg'>Some Kabylake desktop processors may not reach max turbo when running in
HWP mode, even if running under sustained 100% utilization.

This occurs when the HWP.EPP (Energy Performance Preference) is set to
"balance_power" (0x80) -- the default on most systems.

It occurs because the platform BIOS may erroneously enable an
energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not
recommended to be enabled on this SKU.

On the failing systems, this BIOS issue was not discovered when the
desktop motherboard was tested with Windows, because the BIOS also
neglects to provide the ACPI/CPPC table, that Windows requires to enable
HWP, and so Windows runs in legacy P-state mode, where this setting has
no effect.

Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and
so it runs in HWP mode, exposing this incorrect BIOS configuration.

There are several ways to address this problem.

First, Linux can also run in legacy P-state mode on this system.
As intel_pstate is how Linux enables HWP, booting with
"intel_pstate=disable"
will run in acpi-cpufreq/ondemand legacy p-state mode.

Or second, the "performance" governor can be used with intel_pstate,
which will modify HWP.EPP to 0.

Or third, starting in 4.10, the
/sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference
attribute in can be updated from "balance_power" to "performance".

Or fourth, apply this patch, which fixes the erroneous setting of
MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default
configuration to function as designed.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Reviewed-by: Len Brown &lt;len.brown@intel.com&gt;
Cc: 4.6+ &lt;stable@vger.kernel.org&gt; # 4.6+
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</div><div class='diffstat-header'><a href='/cgit.cgi/linux/net-next.git/diff/?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>Diffstat</a> (limited to 'include/drm/drm_agpsupport.h')</div><table summary='diffstat' class='diffstat'>