/* * nv_tco: TCO timer driver for nVidia chipsets. * * (c) Copyright 2005 Google Inc., All Rights Reserved. * * Supported Chipsets: * - MCP51/MCP55 * * (c) Copyright 2000 kernel concepts , All Rights * Reserved. * http://www.kernelconcepts.de * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * * Neither kernel concepts nor Nils Faerber admit liability nor provide * warranty for any of this software. This material is provided * "AS-IS" and at no charge. * * (c) Copyright 2000 kernel concepts * developed for * Jentro AG, Haar/Munich (Germany) * * TCO timer driver for NV chipsets * based on softdog.c by Alan Cox */ /* * Some address definitions for the TCO */ #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */ #define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */ #define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */ /* * TCO Boot Status bit: set on TCO reset, reset by software or standby * power-good (survives reboots), unfortunately this bit is never * set. */ # define TCO_STS_BOOT_STS (1 << 9) /* * first and 2nd timeout status bits, these also survive a warm boot, * and they work, so we use them. */ # define TCO_STS_TCO_INT_STS (1 << 1) # define TCO_STS_TCO2TO_STS (1 << 10) # define TCO_STS_RESET (TCO_STS_BOOT_STS | TCO_STS_TCO2TO_STS | \ TCO_STS_TCO_INT_STS) #define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */ # define TCO_CNT_TCOHALT (1 << 12) #define MCP51_SMBUS_SETUP_B 0xe8 # define MCP51_SMBUS_SETUP_B_TCO_REBOOT (1 << 25) /* * The SMI_EN register is at the base io address + 0x04, * while TCOBASE is + 0x40. */ #define MCP51_SMI_EN(base) ((base) - 0x40 + 0x04) # define MCP51_SMI_EN_TCO ((1 << 4) | (1 << 5)) /cgit.cgi/linux/net-next.git/diff/drivers/usb/host/ohci-ps3.c?id=c8f325a59cfc718d13a50fbc746ed9b415c25e92'>diff
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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2017-02-01 17:45:02 +0000
committerIngo Molnar <mingo@kernel.org>2017-02-01 21:17:49 +0100
commitc8f325a59cfc718d13a50fbc746ed9b415c25e92 (patch)
treed53fbdac9d0781e39a13b2ac6b2bd258cf3b4140 /drivers/usb/host/ohci-ps3.c
parentbf29bddf0417a4783da3b24e8c9e017ac649326f (diff)
efi/fdt: Avoid FDT manipulation after ExitBootServices()
Some AArch64 UEFI implementations disable the MMU in ExitBootServices(), after which unaligned accesses to RAM are no longer supported. Commit: abfb7b686a3e ("efi/libstub/arm*: Pass latest memory map to the kernel") fixed an issue in the memory map handling of the stub FDT code, but inadvertently created an issue with such firmware, by moving some of the FDT manipulation to after the invocation of ExitBootServices(). Given that the stub's libfdt implementation uses the ordinary, accelerated string functions, which rely on hardware handling of unaligned accesses, manipulating the FDT with the MMU off may result in alignment faults. So fix the situation by moving the update_fdt_memmap() call into the callback function invoked by efi_exit_boot_services() right before it calls the ExitBootServices() UEFI service (which is arguably a better place for it anyway) Note that disabling the MMU in ExitBootServices() is not compliant with the UEFI spec, and carries great risk due to the fact that switching from cached to uncached memory accesses halfway through compiler generated code (i.e., involving a stack) can never be done in a way that is architecturally safe. Fixes: abfb7b686a3e ("efi/libstub/arm*: Pass latest memory map to the kernel") Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Riku Voipio <riku.voipio@linaro.org> Cc: <stable@vger.kernel.org> Cc: mark.rutland@arm.com Cc: linux-efi@vger.kernel.org Cc: matt@codeblueprint.co.uk Cc: leif.lindholm@linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1485971102-23330-2-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'drivers/usb/host/ohci-ps3.c')