#ifndef _ASM_GENERIC_CPUTIME_JIFFIES_H #define _ASM_GENERIC_CPUTIME_JIFFIES_H typedef unsigned long __nocast cputime_t; #define cmpxchg_cputime(ptr, old, new) cmpxchg(ptr, old, new) #define cputime_one_jiffy jiffies_to_cputime(1) #define cputime_to_jiffies(__ct) (__force unsigned long)(__ct) #define jiffies_to_cputime(__hz) (__force cputime_t)(__hz) typedef u64 __nocast cputime64_t; #define cputime64_to_jiffies64(__ct) (__force u64)(__ct) #define jiffies64_to_cputime64(__jif) (__force cputime64_t)(__jif) /* * Convert nanoseconds <-> cputime */ #define cputime_to_nsecs(__ct) \ jiffies_to_nsecs(cputime_to_jiffies(__ct)) #define nsecs_to_cputime64(__nsec) \ jiffies64_to_cputime64(nsecs_to_jiffies64(__nsec)) #define nsecs_to_cputime(__nsec) \ jiffies_to_cputime(nsecs_to_jiffies(__nsec)) /* * Convert cputime to microseconds and back. */ #define cputime_to_usecs(__ct) \ jiffies_to_usecs(cputime_to_jiffies(__ct)) #define usecs_to_cputime(__usec) \ jiffies_to_cputime(usecs_to_jiffies(__usec)) #define usecs_to_cputime64(__usec) \ jiffies64_to_cputime64(nsecs_to_jiffies64((__usec) * 1000)) /* * Convert cputime to seconds and back. */ #define cputime_to_secs(jif) (cputime_to_jiffies(jif) / HZ) #define secs_to_cputime(sec) jiffies_to_cputime((sec) * HZ) /* * Convert cputime to timespec and back. */ #define timespec_to_cputime(__val) \ jiffies_to_cputime(timespec_to_jiffies(__val)) #define cputime_to_timespec(__ct,__val) \ jiffies_to_timespec(cputime_to_jiffies(__ct),__val) /* * Convert cputime to timeval and back. */ #define timeval_to_cputime(__val) \ jiffies_to_cputime(timeval_to_jiffies(__val)) #define cputime_to_timeval(__ct,__val) \ jiffies_to_timeval(cputime_to_jiffies(__ct),__val) /* * Convert cputime to clock and back. */ #define cputime_to_clock_t(__ct) \ jiffies_to_clock_t(cputime_to_jiffies(__ct)) #define clock_t_to_cputime(__x) \ jiffies_to_cputime(clock_t_to_jiffies(__x)) /* * Convert cputime64 to clock. */ #define cputime64_to_clock_t(__ct) \ jiffies_64_to_clock_t(cputime64_to_jiffies64(__ct)) #endif 24440b5f1d93e968ee3'>commitdiff
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /include/trace
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include/trace')