#ifndef _ASM_GENERIC_CPUTIME_JIFFIES_H #define _ASM_GENERIC_CPUTIME_JIFFIES_H typedef unsigned long __nocast cputime_t; #define cmpxchg_cputime(ptr, old, new) cmpxchg(ptr, old, new) #define cputime_one_jiffy jiffies_to_cputime(1) #define cputime_to_jiffies(__ct) (__force unsigned long)(__ct) #define jiffies_to_cputime(__hz) (__force cputime_t)(__hz) typedef u64 __nocast cputime64_t; #define cputime64_to_jiffies64(__ct) (__force u64)(__ct) #define jiffies64_to_cputime64(__jif) (__force cputime64_t)(__jif) /* * Convert nanoseconds <-> cputime */ #define cputime_to_nsecs(__ct) \ jiffies_to_nsecs(cputime_to_jiffies(__ct)) #define nsecs_to_cputime64(__nsec) \ jiffies64_to_cputime64(nsecs_to_jiffies64(__nsec)) #define nsecs_to_cputime(__nsec) \ jiffies_to_cputime(nsecs_to_jiffies(__nsec)) /* * Convert cputime to microseconds and back. */ #define cputime_to_usecs(__ct) \ jiffies_to_usecs(cputime_to_jiffies(__ct)) #define usecs_to_cputime(__usec) \ jiffies_to_cputime(usecs_to_jiffies(__usec)) #define usecs_to_cputime64(__usec) \ jiffies64_to_cputime64(nsecs_to_jiffies64((__usec) * 1000)) /* * Convert cputime to seconds and back. */ #define cputime_to_secs(jif) (cputime_to_jiffies(jif) / HZ) #define secs_to_cputime(sec) jiffies_to_cputime((sec) * HZ) /* * Convert cputime to timespec and back. */ #define timespec_to_cputime(__val) \ jiffies_to_cputime(timespec_to_jiffies(__val)) #define cputime_to_timespec(__ct,__val) \ jiffies_to_timespec(cputime_to_jiffies(__ct),__val) /* * Convert cputime to timeval and back. */ #define timeval_to_cputime(__val) \ jiffies_to_cputime(timeval_to_jiffies(__val)) #define cputime_to_timeval(__ct,__val) \ jiffies_to_timeval(cputime_to_jiffies(__ct),__val) /* * Convert cputime to clock and back. */ #define cputime_to_clock_t(__ct) \ jiffies_to_clock_t(cputime_to_jiffies(__ct)) #define clock_t_to_cputime(__x) \ jiffies_to_cputime(clock_t_to_jiffies(__x)) /* * Convert cputime64 to clock. */ #define cputime64_to_clock_t(__ct) \ jiffies_64_to_clock_t(cputime64_to_jiffies64(__ct)) #endif 30305d69fc6963c16003f50d7e8d74b02d0a143'>diff
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authorBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
commit030305d69fc6963c16003f50d7e8d74b02d0a143 (patch)
tree363a4e34d199178769b7e7eeb26ea2620a55847b /sound/soc/intel/boards
parent4d191b1b63c209e37bf27938ef365244d3c41084 (diff)
PCI/ASPM: Handle PCI-to-PCIe bridges as roots of PCIe hierarchies
In a struct pcie_link_state, link->root points to the pcie_link_state of the root of the PCIe hierarchy. For the topmost link, this points to itself (link->root = link). For others, we copy the pointer from the parent (link->root = link->parent->root). Previously we recognized that Root Ports originated PCIe hierarchies, but we treated PCI/PCI-X to PCIe Bridges as being in the middle of the hierarchy, and when we tried to copy the pointer from link->parent->root, there was no parent, and we dereferenced a NULL pointer: BUG: unable to handle kernel NULL pointer dereference at 0000000000000090 IP: [<ffffffff9e424350>] pcie_aspm_init_link_state+0x170/0x820 Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just like Root Ports do, so link->root for these devices should also point to itself. Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges") Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411 Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181 Tested-by: lists@ssl-mail.com Tested-by: Jayachandran C. <jnair@caviumnetworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.2+
Diffstat (limited to 'sound/soc/intel/boards')