#ifndef __ASM_GENERIC_IRQFLAGS_H #define __ASM_GENERIC_IRQFLAGS_H /* * All architectures should implement at least the first two functions, * usually inline assembly will be the best way. */ #ifndef ARCH_IRQ_DISABLED #define ARCH_IRQ_DISABLED 0 #define ARCH_IRQ_ENABLED 1 #endif /* read interrupt enabled status */ #ifndef arch_local_save_flags unsigned long arch_local_save_flags(void); #endif /* set interrupt enabled status */ #ifndef arch_local_irq_restore void arch_local_irq_restore(unsigned long flags); #endif /* get status and disable interrupts */ #ifndef arch_local_irq_save static inline unsigned long arch_local_irq_save(void) { unsigned long flags; flags = arch_local_save_flags(); arch_local_irq_restore(ARCH_IRQ_DISABLED); return flags; } #endif /* test flags */ #ifndef arch_irqs_disabled_flags static inline int arch_irqs_disabled_flags(unsigned long flags) { return flags == ARCH_IRQ_DISABLED; } #endif /* unconditionally enable interrupts */ #ifndef arch_local_irq_enable static inline void arch_local_irq_enable(void) { arch_local_irq_restore(ARCH_IRQ_ENABLED); } #endif /* unconditionally disable interrupts */ #ifndef arch_local_irq_disable static inline void arch_local_irq_disable(void) { arch_local_irq_restore(ARCH_IRQ_DISABLED); } #endif /* test hardware interrupt enable bit */ #ifndef arch_irqs_disabled static inline int arch_irqs_disabled(void) { return arch_irqs_disabled_flags(arch_local_save_flags()); } #endif #endif /* __ASM_GENERIC_IRQFLAGS_H */ /tr>
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authorBorislav Petkov <bp@suse.de>2017-01-20 21:29:40 +0100
committerThomas Gleixner <tglx@linutronix.de>2017-01-23 09:39:55 +0100
commitc26665ab5c49ad3e142e0f054ca3204f259ba09c (patch)
tree3bab11918e18e9d25ef7544dba05cdf39d1abec5 /net/wireless/trace.h
parent7a308bb3016f57e5be11a677d15b821536419d36 (diff)
x86/microcode/intel: Drop stashed AP patch pointer optimization
This was meant to save us the scanning of the microcode containter in the initrd since the first AP had already done that but it can also hurt us: Imagine a single hyperthreaded CPU (Intel(R) Atom(TM) CPU N270, for example) which updates the microcode on the BSP but since the microcode engine is shared between the two threads, the update on CPU1 doesn't happen because it has already happened on CPU0 and we don't find a newer microcode revision on CPU1. Which doesn't set the intel_ucode_patch pointer and at initrd jettisoning time we don't save the microcode patch for later application. Now, when we suspend to RAM, the loaded microcode gets cleared so we need to reload but there's no patch saved in the cache. Removing the optimization fixes this issue and all is fine and dandy. Fixes: 06b8534cb728 ("x86/microcode: Rework microcode loading") Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20170120202955.4091-2-bp@alien8.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'net/wireless/trace.h')