/* * ARTPEC-6 clock controller indexes * * Copyright 2016 Axis Comunications AB. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H #define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H #define ARTPEC6_CLK_CPU 0 #define ARTPEC6_CLK_CPU_PERIPH 1 #define ARTPEC6_CLK_NAND_CLKA 2 #define ARTPEC6_CLK_NAND_CLKB 3 #define ARTPEC6_CLK_ETH_ACLK 4 #define ARTPEC6_CLK_DMA_ACLK 5 #define ARTPEC6_CLK_PTP_REF 6 #define ARTPEC6_CLK_SD_PCLK 7 #define ARTPEC6_CLK_SD_IMCLK 8 #define ARTPEC6_CLK_I2S_HST 9 #define ARTPEC6_CLK_I2S0_CLK 10 #define ARTPEC6_CLK_I2S1_CLK 11 #define ARTPEC6_CLK_UART_PCLK 12 #define ARTPEC6_CLK_UART_REFCLK 13 #define ARTPEC6_CLK_I2C 14 #define ARTPEC6_CLK_SPI_PCLK 15 #define ARTPEC6_CLK_SPI_SSPCLK 16 #define ARTPEC6_CLK_SYS_TIMER 17 #define ARTPEC6_CLK_FRACDIV_IN 18 #define ARTPEC6_CLK_DBG_PCLK 19 /* This must be the highest clock index plus one. */ #define ARTPEC6_CLK_NUMCLOCKS 20 #endif er net-next plumbingsTobias Klauser
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authorColin Ian King <colin.king@canonical.com>2017-01-11 15:36:20 +0000
committerMark Brown <broonie@kernel.org>2017-01-18 16:32:44 +0000
commitb98acbff9a05b371c5f0ca6e44a3af8ce9274379 (patch)
treed6835885f859a456e62ce93621041138d6a54f9b /net/ipv4/proc.c
parentd00b74613fb18dfd0a5aa99270ee2e72d5c808d7 (diff)
regulator: twl6030: fix range comparison, allowing vsel = 59
The range min_uV > 1350000 && min_uV <= 150000 is never reachable because of a typo in the previous range check and hence vsel = 59 is never reached. Fix the previous range check to enable the vsel = 59 setting. Fixes CoverityScan CID#728454 ("Logially dead code") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'net/ipv4/proc.c')