/* * BSD LICENSE * * Copyright(c) 2015 Broadcom Corporation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * Neither the name of Broadcom Corporation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _CLOCK_BCM_NS2_H #define _CLOCK_BCM_NS2_H /* GENPLL SCR clock channel ID */ #define BCM_NS2_GENPLL_SCR 0 #define BCM_NS2_GENPLL_SCR_SCR_CLK 1 #define BCM_NS2_GENPLL_SCR_FS_CLK 2 #define BCM_NS2_GENPLL_SCR_AUDIO_CLK 3 #define BCM_NS2_GENPLL_SCR_CH3_UNUSED 4 #define BCM_NS2_GENPLL_SCR_CH4_UNUSED 5 #define BCM_NS2_GENPLL_SCR_CH5_UNUSED 6 /* GENPLL SW clock channel ID */ #define BCM_NS2_GENPLL_SW 0 #define BCM_NS2_GENPLL_SW_RPE_CLK 1 #define BCM_NS2_GENPLL_SW_250_CLK 2 #define BCM_NS2_GENPLL_SW_NIC_CLK 3 #define BCM_NS2_GENPLL_SW_CHIMP_CLK 4 #define BCM_NS2_GENPLL_SW_PORT_CLK 5 #define BCM_NS2_GENPLL_SW_SDIO_CLK 6 /* LCPLL DDR clock channel ID */ #define BCM_NS2_LCPLL_DDR 0 #define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK 1 #define BCM_NS2_LCPLL_DDR_DDR_CLK 2 #define BCM_NS2_LCPLL_DDR_CH2_UNUSED 3 #define BCM_NS2_LCPLL_DDR_CH3_UNUSED 4 #define BCM_NS2_LCPLL_DDR_CH4_UNUSED 5 #define BCM_NS2_LCPLL_DDR_CH5_UNUSED 6 /* LCPLL PORTS clock channel ID */ #define BCM_NS2_LCPLL_PORTS 0 #define BCM_NS2_LCPLL_PORTS_WAN_CLK 1 #define BCM_NS2_LCPLL_PORTS_RGMII_CLK 2 #define BCM_NS2_LCPLL_PORTS_CH2_UNUSED 3 #define BCM_NS2_LCPLL_PORTS_CH3_UNUSED 4 #define BCM_NS2_LCPLL_PORTS_CH4_UNUSED 5 #define BCM_NS2_LCPLL_PORTS_CH5_UNUSED 6 #endif /* _CLOCK_BCM_NS2_H */ c94eca944be9cd23dfc752'>root/sound/soc/intel/boards/skl_nau88l25_ssm4567.c
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authorChristoph Hellwig <hch@lst.de>2017-01-30 13:15:41 +0100
committerBjorn Helgaas <bhelgaas@google.com>2017-02-02 10:35:46 -0600
commitdfef358bd1beb4e7b5c94eca944be9cd23dfc752 (patch)
treeb9a2afb38a4c2ac8ad31f49ec0d71fe9e5b1994c /sound/soc/intel/boards/skl_nau88l25_ssm4567.c
parent030305d69fc6963c16003f50d7e8d74b02d0a143 (diff)
PCI/MSI: Don't apply affinity if there aren't enough vectors left
Bart reported a problem wіth an out of bounds access in the low-level IRQ affinity code, which we root caused to the qla2xxx driver assigning all its MSI-X vectors to the pre and post vectors, and not having any left for the actually spread IRQs. Fix this issue by not asking for affinity assignment when there are no vectors to assign left. Fixes: 402723ad5c62 ("PCI/MSI: Provide pci_alloc_irq_vectors_affinity()") Link: https://lkml.kernel.org/r/1485359225.3093.3.camel@sandisk.com Reported-by: Bart Van Assche <bart.vanassche@sandisk.com> Tested-by: Bart Van Assche <bart.vanassche@sandisk.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'sound/soc/intel/boards/skl_nau88l25_ssm4567.c')