/*
* This header provides constants for Samsung audio subsystem
* clock controller.
*
* The constants defined in this header are being used in dts
* and exynos audss driver.
*/
#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
#define EXYNOS_MOUT_AUDSS 0
#define EXYNOS_MOUT_I2S 1
#define EXYNOS_DOUT_SRP 2
#define EXYNOS_DOUT_AUD_BUS 3
#define EXYNOS_DOUT_I2S 4
#define EXYNOS_SRP_CLK 5
#define EXYNOS_I2S_BUS 6
#define EXYNOS_SCLK_I2S 7
#define EXYNOS_PCM_BUS 8
#define EXYNOS_SCLK_PCM 9
#define EXYNOS_ADMA 10
#define EXYNOS_AUDSS_MAX_CLKS 11
#endif
it'>
sh_eth: rename EESIPR bits
Since the commit b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth")
the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with
the *enum* declaring the EESR bits (interrupt status) WRT bit naming and
formatting. I'd like to restore the consistency by using EESIPR as the bit
name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the
bits according to the available Renesas SH77{34|63} manuals; additionally,
reconstruct couple names using the EESR bit declaration above...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
