/* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Copyright (c) 2016 Krzysztof Kozlowski * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Device Tree binding constants for Exynos5421 clock controller. */ #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H /* core clocks */ #define CLK_FIN_PLL 1 #define CLK_FOUT_APLL 2 #define CLK_FOUT_CPLL 3 #define CLK_FOUT_MPLL 4 #define CLK_FOUT_BPLL 5 #define CLK_FOUT_KPLL 6 #define CLK_FOUT_EPLL 7 /* gate for special clocks (sclk) */ #define CLK_SCLK_UART0 128 #define CLK_SCLK_UART1 129 #define CLK_SCLK_UART2 130 #define CLK_SCLK_UART3 131 #define CLK_SCLK_MMC0 132 #define CLK_SCLK_MMC1 133 #define CLK_SCLK_MMC2 134 #define CLK_SCLK_USBD300 150 #define CLK_SCLK_USBD301 151 #define CLK_SCLK_USBPHY300 152 #define CLK_SCLK_USBPHY301 153 #define CLK_SCLK_PWM 155 /* gate clocks */ #define CLK_UART0 257 #define CLK_UART1 258 #define CLK_UART2 259 #define CLK_I2C0 261 #define CLK_I2C1 262 #define CLK_I2C2 263 #define CLK_I2C3 264 #define CLK_USI0 265 #define CLK_USI1 266 #define CLK_USI2 267 #define CLK_USI3 268 #define CLK_UART3 260 #define CLK_PWM 279 #define CLK_MCT 315 #define CLK_WDT 316 #define CLK_RTC 317 #define CLK_TMU 318 #define CLK_MMC0 351 #define CLK_MMC1 352 #define CLK_MMC2 353 #define CLK_PDMA0 362 #define CLK_PDMA1 363 #define CLK_USBH20 365 #define CLK_USBD300 366 #define CLK_USBD301 367 #define CLK_SSS 471 #define CLK_NR_CLKS 512 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ rivate-remove&id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>refslogtreecommitdiff
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authorSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>2017-02-03 14:18:39 -0800
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2017-02-04 00:11:08 +0100
commit6e978b22efa1db9f6e71b24440b5f1d93e968ee3 (patch)
treec666f7a26b860674848949e39a610222b0723f89 /sound/soc/codecs/tlv320aic23.c
parent3c223c19aea85d3dda1416c187915f4a30b04b1f (diff)
cpufreq: intel_pstate: Disable energy efficiency optimization
Some Kabylake desktop processors may not reach max turbo when running in HWP mode, even if running under sustained 100% utilization. This occurs when the HWP.EPP (Energy Performance Preference) is set to "balance_power" (0x80) -- the default on most systems. It occurs because the platform BIOS may erroneously enable an energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not recommended to be enabled on this SKU. On the failing systems, this BIOS issue was not discovered when the desktop motherboard was tested with Windows, because the BIOS also neglects to provide the ACPI/CPPC table, that Windows requires to enable HWP, and so Windows runs in legacy P-state mode, where this setting has no effect. Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and so it runs in HWP mode, exposing this incorrect BIOS configuration. There are several ways to address this problem. First, Linux can also run in legacy P-state mode on this system. As intel_pstate is how Linux enables HWP, booting with "intel_pstate=disable" will run in acpi-cpufreq/ondemand legacy p-state mode. Or second, the "performance" governor can be used with intel_pstate, which will modify HWP.EPP to 0. Or third, starting in 4.10, the /sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference attribute in can be updated from "balance_power" to "performance". Or fourth, apply this patch, which fixes the erroneous setting of MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default configuration to function as designed. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Len Brown <len.brown@intel.com> Cc: 4.6+ <stable@vger.kernel.org> # 4.6+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'sound/soc/codecs/tlv320aic23.c')