/*
 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __DT_BINDINGS_CLOCK_IMX21_H
#define __DT_BINDINGS_CLOCK_IMX21_H

#define IMX21_CLK_DUMMY			0
#define IMX21_CLK_CKIL			1
#define IMX21_CLK_CKIH			2
#define IMX21_CLK_FPM			3
#define IMX21_CLK_CKIH_DIV1P5		4
#define IMX21_CLK_MPLL_GATE		5
#define IMX21_CLK_SPLL_GATE		6
#define IMX21_CLK_FPM_GATE		7
#define IMX21_CLK_CKIH_GATE		8
#define IMX21_CLK_MPLL_OSC_SEL		9
#define IMX21_CLK_IPG			10
#define IMX21_CLK_HCLK			11
#define IMX21_CLK_MPLL_SEL		12
#define IMX21_CLK_SPLL_SEL		13
#define IMX21_CLK_SSI1_SEL		14
#define IMX21_CLK_SSI2_SEL		15
#define IMX21_CLK_USB_DIV		16
#define IMX21_CLK_FCLK			17
#define IMX21_CLK_MPLL			18
#define IMX21_CLK_SPLL			19
#define IMX21_CLK_NFC_DIV		20
#define IMX21_CLK_SSI1_DIV		21
#define IMX21_CLK_SSI2_DIV		22
#define IMX21_CLK_PER1			23
#define IMX21_CLK_PER2			24
#define IMX21_CLK_PER3			25
#define IMX21_CLK_PER4			26
#define IMX21_CLK_UART1_IPG_GATE	27
#define IMX21_CLK_UART2_IPG_GATE	28
#define IMX21_CLK_UART3_IPG_GATE	29
#define IMX21_CLK_UART4_IPG_GATE	30
#define IMX21_CLK_CSPI1_IPG_GATE	31
#define IMX21_CLK_CSPI2_IPG_GATE	32
#define IMX21_CLK_SSI1_GATE		33
#define IMX21_CLK_SSI2_GATE		34
#define IMX21_CLK_SDHC1_IPG_GATE	35
#define IMX21_CLK_SDHC2_IPG_GATE	36
#define IMX21_CLK_GPIO_GATE		37
#define IMX21_CLK_I2C_GATE		38
#define IMX21_CLK_DMA_GATE		39
#define IMX21_CLK_USB_GATE		40
#define IMX21_CLK_EMMA_GATE		41
#define IMX21_CLK_SSI2_BAUD_GATE	42
#define IMX21_CLK_SSI1_BAUD_GATE	43
#define IMX21_CLK_LCDC_IPG_GATE		44
#define IMX21_CLK_NFC_GATE		45
#define IMX21_CLK_LCDC_HCLK_GATE	46
#define IMX21_CLK_PER4_GATE		47
#define IMX21_CLK_BMI_GATE		48
#define IMX21_CLK_USB_HCLK_GATE		49
#define IMX21_CLK_SLCDC_GATE		50
#define IMX21_CLK_SLCDC_HCLK_GATE	51
#define IMX21_CLK_EMMA_HCLK_GATE	52
#define IMX21_CLK_BROM_GATE		53
#define IMX21_CLK_DMA_HCLK_GATE		54
#define IMX21_CLK_CSI_HCLK_GATE		55
#define IMX21_CLK_CSPI3_IPG_GATE	56
#define IMX21_CLK_WDOG_GATE		57
#define IMX21_CLK_GPT1_IPG_GATE		58
#define IMX21_CLK_GPT2_IPG_GATE		59
#define IMX21_CLK_GPT3_IPG_GATE		60
#define IMX21_CLK_PWM_IPG_GATE		61
#define IMX21_CLK_RTC_GATE		62
#define IMX21_CLK_KPP_GATE		63
#define IMX21_CLK_OWIRE_GATE		64
#define IMX21_CLK_MAX			65

#endif
/net-next.git/log/include/dt-bindings/clock/exynos5250.h'>
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<option value='grep'>log msg</option>
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</td></tr></table>
<div class='path'>path: <a href='/cgit.cgi/linux/net-next.git/commit/?h=nds-private-remove&amp;id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>root</a>/<a href='/cgit.cgi/linux/net-next.git/commit/include?h=nds-private-remove&amp;id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>include</a>/<a href='/cgit.cgi/linux/net-next.git/commit/include/dt-bindings?h=nds-private-remove&amp;id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>dt-bindings</a>/<a href='/cgit.cgi/linux/net-next.git/commit/include/dt-bindings/clock?h=nds-private-remove&amp;id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>clock</a>/<a href='/cgit.cgi/linux/net-next.git/commit/include/dt-bindings/clock/exynos5250.h?h=nds-private-remove&amp;id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>exynos5250.h</a></div><div class='content'><div class='cgit-panel'><b>diff options</b><form method='get'><input type='hidden' name='h' value='nds-private-remove'/><input type='hidden' name='id' value='6e978b22efa1db9f6e71b24440b5f1d93e968ee3'/><table><tr><td colspan='2'/></tr><tr><td class='label'>context:</td><td class='ctrl'><select name='context' onchange='this.form.submit();'><option value='1'>1</option><option value='2'>2</option><option value='3' selected='selected'>3</option><option value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><table summary='commit info' class='commit-info'>
<tr><th>author</th><td>Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;</td><td class='right'>2017-02-03 14:18:39 -0800</td></tr>
<tr><th>committer</th><td>Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;</td><td class='right'>2017-02-04 00:11:08 +0100</td></tr>
<tr><th>commit</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/include/dt-bindings/clock/exynos5250.h?h=nds-private-remove&amp;id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>6e978b22efa1db9f6e71b24440b5f1d93e968ee3</a> (<a href='/cgit.cgi/linux/net-next.git/patch/include/dt-bindings/clock/exynos5250.h?id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>patch</a>)</td></tr>
<tr><th>tree</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/tree/?h=nds-private-remove&amp;id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>c666f7a26b860674848949e39a610222b0723f89</a> /<a href='/cgit.cgi/linux/net-next.git/tree/include/dt-bindings/clock/exynos5250.h?h=nds-private-remove&amp;id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>include/dt-bindings/clock/exynos5250.h</a></td></tr>
<tr><th>parent</th><td colspan='2' class='oid'><a href='/cgit.cgi/linux/net-next.git/commit/include/dt-bindings/clock/exynos5250.h?h=nds-private-remove&amp;id=3c223c19aea85d3dda1416c187915f4a30b04b1f'>3c223c19aea85d3dda1416c187915f4a30b04b1f</a> (<a href='/cgit.cgi/linux/net-next.git/diff/include/dt-bindings/clock/exynos5250.h?h=nds-private-remove&amp;id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3&amp;id2=3c223c19aea85d3dda1416c187915f4a30b04b1f'>diff</a>)</td></tr></table>
<div class='commit-subject'>cpufreq: intel_pstate: Disable energy efficiency optimization</div><div class='commit-msg'>Some Kabylake desktop processors may not reach max turbo when running in
HWP mode, even if running under sustained 100% utilization.

This occurs when the HWP.EPP (Energy Performance Preference) is set to
"balance_power" (0x80) -- the default on most systems.

It occurs because the platform BIOS may erroneously enable an
energy-efficiency setting -- MSR_IA32_POWER_CTL BIT-EE, which is not
recommended to be enabled on this SKU.

On the failing systems, this BIOS issue was not discovered when the
desktop motherboard was tested with Windows, because the BIOS also
neglects to provide the ACPI/CPPC table, that Windows requires to enable
HWP, and so Windows runs in legacy P-state mode, where this setting has
no effect.

Linux' intel_pstate driver does not require ACPI/CPPC to enable HWP, and
so it runs in HWP mode, exposing this incorrect BIOS configuration.

There are several ways to address this problem.

First, Linux can also run in legacy P-state mode on this system.
As intel_pstate is how Linux enables HWP, booting with
"intel_pstate=disable"
will run in acpi-cpufreq/ondemand legacy p-state mode.

Or second, the "performance" governor can be used with intel_pstate,
which will modify HWP.EPP to 0.

Or third, starting in 4.10, the
/sys/devices/system/cpu/cpufreq/policy*/energy_performance_preference
attribute in can be updated from "balance_power" to "performance".

Or fourth, apply this patch, which fixes the erroneous setting of
MSR_IA32_POWER_CTL BIT_EE on this model, allowing the default
configuration to function as designed.

Signed-off-by: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Reviewed-by: Len Brown &lt;len.brown@intel.com&gt;
Cc: 4.6+ &lt;stable@vger.kernel.org&gt; # 4.6+
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</div><div class='diffstat-header'><a href='/cgit.cgi/linux/net-next.git/diff/?h=nds-private-remove&amp;id=6e978b22efa1db9f6e71b24440b5f1d93e968ee3'>Diffstat</a> (limited to 'include/dt-bindings/clock/exynos5250.h')</div><table summary='diffstat' class='diffstat'>