/* * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. * * They are roughly ordered as: * - external clocks * - PLLs * - muxes/dividers in the order they appear in the jz4740 programmers manual * - gates in order of their bit in the CLKGR* registers */ #ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ #define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ #define JZ4740_CLK_EXT 0 #define JZ4740_CLK_RTC 1 #define JZ4740_CLK_PLL 2 #define JZ4740_CLK_PLL_HALF 3 #define JZ4740_CLK_CCLK 4 #define JZ4740_CLK_HCLK 5 #define JZ4740_CLK_PCLK 6 #define JZ4740_CLK_MCLK 7 #define JZ4740_CLK_LCD 8 #define JZ4740_CLK_LCD_PCLK 9 #define JZ4740_CLK_I2S 10 #define JZ4740_CLK_SPI 11 #define JZ4740_CLK_MMC 12 #define JZ4740_CLK_UHC 13 #define JZ4740_CLK_UDC 14 #define JZ4740_CLK_UART0 15 #define JZ4740_CLK_UART1 16 #define JZ4740_CLK_DMA 17 #define JZ4740_CLK_IPU 18 #define JZ4740_CLK_ADC 19 #define JZ4740_CLK_I2C 20 #define JZ4740_CLK_AIC 21 #endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ on value='emaclite-cleanup'>emaclite-cleanup net-next plumbingsTobias Klauser
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authorMarcel J.E. Mol <marcel@mesa.nl>2017-01-30 19:26:40 +0100
committerJohan Hovold <johan@kernel.org>2017-01-31 17:27:04 +0100
commitd07830db1bdb254e4b50d366010b219286b8c937 (patch)
tree354d7fca237fa3d7e7e63c2196eaa4e1086838ea /net/wireless/wext-core.c
parent5d03a2fd2292e71936c4235885c35ccc3c94695b (diff)
USB: serial: pl2303: add ATEN device ID
Seems that ATEN serial-to-usb devices using pl2303 exist with different device ids. This patch adds a missing device ID so it is recognised by the driver. Signed-off-by: Marcel J.E. Mol <marcel@mesa.nl> Cc: stable <stable@vger.kernel.org> Signed-off-by: Johan Hovold <johan@kernel.org>
Diffstat (limited to 'net/wireless/wext-core.c')