/* * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. * * They are roughly ordered as: * - external clocks * - PLLs * - muxes/dividers in the order they appear in the jz4780 programmers manual * - gates in order of their bit in the CLKGR* registers */ #ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ #define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ #define JZ4780_CLK_EXCLK 0 #define JZ4780_CLK_RTCLK 1 #define JZ4780_CLK_APLL 2 #define JZ4780_CLK_MPLL 3 #define JZ4780_CLK_EPLL 4 #define JZ4780_CLK_VPLL 5 #define JZ4780_CLK_OTGPHY 6 #define JZ4780_CLK_SCLKA 7 #define JZ4780_CLK_CPUMUX 8 #define JZ4780_CLK_CPU 9 #define JZ4780_CLK_L2CACHE 10 #define JZ4780_CLK_AHB0 11 #define JZ4780_CLK_AHB2PMUX 12 #define JZ4780_CLK_AHB2 13 #define JZ4780_CLK_PCLK 14 #define JZ4780_CLK_DDR 15 #define JZ4780_CLK_VPU 16 #define JZ4780_CLK_I2SPLL 17 #define JZ4780_CLK_I2S 18 #define JZ4780_CLK_LCD0PIXCLK 19 #define JZ4780_CLK_LCD1PIXCLK 20 #define JZ4780_CLK_MSCMUX 21 #define JZ4780_CLK_MSC0 22 #define JZ4780_CLK_MSC1 23 #define JZ4780_CLK_MSC2 24 #define JZ4780_CLK_UHC 25 #define JZ4780_CLK_SSIPLL 26 #define JZ4780_CLK_SSI 27 #define JZ4780_CLK_CIMMCLK 28 #define JZ4780_CLK_PCMPLL 29 #define JZ4780_CLK_PCM 30 #define JZ4780_CLK_GPU 31 #define JZ4780_CLK_HDMI 32 #define JZ4780_CLK_BCH 33 #define JZ4780_CLK_NEMC 34 #define JZ4780_CLK_OTG0 35 #define JZ4780_CLK_SSI0 36 #define JZ4780_CLK_SMB0 37 #define JZ4780_CLK_SMB1 38 #define JZ4780_CLK_SCC 39 #define JZ4780_CLK_AIC 40 #define JZ4780_CLK_TSSI0 41 #define JZ4780_CLK_OWI 42 #define JZ4780_CLK_KBC 43 #define JZ4780_CLK_SADC 44 #define JZ4780_CLK_UART0 45 #define JZ4780_CLK_UART1 46 #define JZ4780_CLK_UART2 47 #define JZ4780_CLK_UART3 48 #define JZ4780_CLK_SSI1 49 #define JZ4780_CLK_SSI2 50 #define JZ4780_CLK_PDMA 51 #define JZ4780_CLK_GPS 52 #define JZ4780_CLK_MAC 53 #define JZ4780_CLK_SMB2 54 #define JZ4780_CLK_CIM 55 #define JZ4780_CLK_LCD 56 #define JZ4780_CLK_TVE 57 #define JZ4780_CLK_IPU 58 #define JZ4780_CLK_DDR0 59 #define JZ4780_CLK_DDR1 60 #define JZ4780_CLK_SMB3 61 #define JZ4780_CLK_TSSI1 62 #define JZ4780_CLK_COMPRESS 63 #define JZ4780_CLK_AIC1 64 #define JZ4780_CLK_GPVLC 65 #define JZ4780_CLK_OTG1 66 #define JZ4780_CLK_UART4 67 #define JZ4780_CLK_AHBMON 68 #define JZ4780_CLK_SMB4 69 #define JZ4780_CLK_DES 70 #define JZ4780_CLK_X2D 71 #define JZ4780_CLK_CORE1 72 #endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ ='range'>range
path: root/include/rdma/ib_cache.h
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authorIago Abal <mail@iagoabal.eu>2017-01-11 14:00:21 +0100
committerVinod Koul <vinod.koul@intel.com>2017-01-25 15:35:11 +0530
commit91539eb1fda2d530d3b268eef542c5414e54bf1a (patch)
tree960f5ca6342ad20837aff18aad6e8ecd7da32fd6 /include/rdma/ib_cache.h
parent6610d0edf6dc7ee97e46ab3a538a565c79d26199 (diff)
dmaengine: pl330: fix double lock
The static bug finder EBA (http://www.iagoabal.eu/eba/) reported the following double-lock bug: Double lock: 1. spin_lock_irqsave(pch->lock, flags) at pl330_free_chan_resources:2236; 2. call to function `pl330_release_channel' immediately after; 3. call to function `dma_pl330_rqcb' in line 1753; 4. spin_lock_irqsave(pch->lock, flags) at dma_pl330_rqcb:1505. I have fixed it as suggested by Marek Szyprowski. First, I have replaced `pch->lock' with `pl330->lock' in functions `pl330_alloc_chan_resources' and `pl330_free_chan_resources'. This avoids the double-lock by acquiring a different lock than `dma_pl330_rqcb'. NOTE that, as a result, `pl330_free_chan_resources' executes `list_splice_tail_init' on `pch->work_list' under lock `pl330->lock', whereas in the rest of the code `pch->work_list' is protected by `pch->lock'. I don't know if this may cause race conditions. Similarly `pch->cyclic' is written by `pl330_alloc_chan_resources' under `pl330->lock' but read by `pl330_tx_submit' under `pch->lock'. Second, I have removed locking from `pl330_request_channel' and `pl330_release_channel' functions. Function `pl330_request_channel' is only called from `pl330_alloc_chan_resources', so the lock is already held. Function `pl330_release_channel' is called from `pl330_free_chan_resources', which already holds the lock, and from `pl330_del'. Function `pl330_del' is called in an error path of `pl330_probe' and at the end of `pl330_remove', but I assume that there cannot be concurrent accesses to the protected data at those points. Signed-off-by: Iago Abal <mail@iagoabal.eu> Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'include/rdma/ib_cache.h')