/* * Copyright (c) 2015 Vladimir Zapolskiy * * This code is released using a dual license strategy: BSD/GPL * You can choose the licence that better fits your requirements. * * Released under the terms of 3-clause BSD License * Released under the terms of GNU General Public License Version 2.0 * */ #ifndef __DT_BINDINGS_LPC32XX_CLOCK_H #define __DT_BINDINGS_LPC32XX_CLOCK_H /* LPC32XX System Control Block clocks */ #define LPC32XX_CLK_RTC 1 #define LPC32XX_CLK_DMA 2 #define LPC32XX_CLK_MLC 3 #define LPC32XX_CLK_SLC 4 #define LPC32XX_CLK_LCD 5 #define LPC32XX_CLK_MAC 6 #define LPC32XX_CLK_SD 7 #define LPC32XX_CLK_DDRAM 8 #define LPC32XX_CLK_SSP0 9 #define LPC32XX_CLK_SSP1 10 #define LPC32XX_CLK_UART3 11 #define LPC32XX_CLK_UART4 12 #define LPC32XX_CLK_UART5 13 #define LPC32XX_CLK_UART6 14 #define LPC32XX_CLK_IRDA 15 #define LPC32XX_CLK_I2C1 16 #define LPC32XX_CLK_I2C2 17 #define LPC32XX_CLK_TIMER0 18 #define LPC32XX_CLK_TIMER1 19 #define LPC32XX_CLK_TIMER2 20 #define LPC32XX_CLK_TIMER3 21 #define LPC32XX_CLK_TIMER4 22 #define LPC32XX_CLK_TIMER5 23 #define LPC32XX_CLK_WDOG 24 #define LPC32XX_CLK_I2S0 25 #define LPC32XX_CLK_I2S1 26 #define LPC32XX_CLK_SPI1 27 #define LPC32XX_CLK_SPI2 28 #define LPC32XX_CLK_MCPWM 29 #define LPC32XX_CLK_HSTIMER 30 #define LPC32XX_CLK_KEY 31 #define LPC32XX_CLK_PWM1 32 #define LPC32XX_CLK_PWM2 33 #define LPC32XX_CLK_ADC 34 #define LPC32XX_CLK_HCLK_PLL 35 #define LPC32XX_CLK_PERIPH 36 /* LPC32XX USB clocks */ #define LPC32XX_USB_CLK_I2C 1 #define LPC32XX_USB_CLK_DEVICE 2 #define LPC32XX_USB_CLK_HOST 3 #endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */ net-next.git/refs/?id=1a0bee6c1e788218fd1d141db320db970aace7f0'>refslogtreecommitdiff
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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2017-01-29 15:07:34 +0300
committerDavid S. Miller <davem@davemloft.net>2017-01-30 22:05:43 -0500
commit1a0bee6c1e788218fd1d141db320db970aace7f0 (patch)
tree46c4116bc8ef4a7df718516a648597d9e21c15f1 /tools/perf/pmu-events/arch/x86/westmereex/cache.json
parent63c190429020a9701b42887ac22c28f287f1762f (diff)
sh_eth: rename EESIPR bits
Since the commit b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth") the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with the *enum* declaring the EESR bits (interrupt status) WRT bit naming and formatting. I'd like to restore the consistency by using EESIPR as the bit name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the bits according to the available Renesas SH77{34|63} manuals; additionally, reconstruct couple names using the EESR bit declaration above... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/westmereex/cache.json')