/* * Copyright (c) 2014 LSI Corporation * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. */ #ifndef _DT_BINDINGS_CLK_AXM5516_H #define _DT_BINDINGS_CLK_AXM5516_H #define AXXIA_CLK_FAB_PLL 0 #define AXXIA_CLK_CPU_PLL 1 #define AXXIA_CLK_SYS_PLL 2 #define AXXIA_CLK_SM0_PLL 3 #define AXXIA_CLK_SM1_PLL 4 #define AXXIA_CLK_FAB_DIV 5 #define AXXIA_CLK_SYS_DIV 6 #define AXXIA_CLK_NRCP_DIV 7 #define AXXIA_CLK_CPU0_DIV 8 #define AXXIA_CLK_CPU1_DIV 9 #define AXXIA_CLK_CPU2_DIV 10 #define AXXIA_CLK_CPU3_DIV 11 #define AXXIA_CLK_PER_DIV 12 #define AXXIA_CLK_MMC_DIV 13 #define AXXIA_CLK_FAB 14 #define AXXIA_CLK_SYS 15 #define AXXIA_CLK_NRCP 16 #define AXXIA_CLK_CPU0 17 #define AXXIA_CLK_CPU1 18 #define AXXIA_CLK_CPU2 19 #define AXXIA_CLK_CPU3 20 #define AXXIA_CLK_PER 21 #define AXXIA_CLK_MMC 22 #endif '/> net-next plumbingsTobias Klauser
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authorBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-01-27 15:00:45 -0600
commit030305d69fc6963c16003f50d7e8d74b02d0a143 (patch)
tree363a4e34d199178769b7e7eeb26ea2620a55847b /tools/perf/scripts
parent4d191b1b63c209e37bf27938ef365244d3c41084 (diff)
PCI/ASPM: Handle PCI-to-PCIe bridges as roots of PCIe hierarchies
In a struct pcie_link_state, link->root points to the pcie_link_state of the root of the PCIe hierarchy. For the topmost link, this points to itself (link->root = link). For others, we copy the pointer from the parent (link->root = link->parent->root). Previously we recognized that Root Ports originated PCIe hierarchies, but we treated PCI/PCI-X to PCIe Bridges as being in the middle of the hierarchy, and when we tried to copy the pointer from link->parent->root, there was no parent, and we dereferenced a NULL pointer: BUG: unable to handle kernel NULL pointer dereference at 0000000000000090 IP: [<ffffffff9e424350>] pcie_aspm_init_link_state+0x170/0x820 Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just like Root Ports do, so link->root for these devices should also point to itself. Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges") Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411 Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181 Tested-by: lists@ssl-mail.com Tested-by: Jayachandran C. <jnair@caviumnetworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.2+
Diffstat (limited to 'tools/perf/scripts')